Intel AI5VG Chipset Features Setup, Bank DRAM Timing, DRAM Read Pipeline, Sustained 3T Write

Chapter 7 LANDesk User Guide

6.5 Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.

ROM PCI/ISA BIOS

CHIPSET FEATURES SETUP

AWARD SOFTWARE INC.

Bank 0/1 DRAM Timing	: 60ns	OnChip USB		: Disabled
Bank 2/3 DRAM Timing	: 60ns
Bank 4/5 DRAM Timing	: 60ns
DRAM Read Pipeline	: Enabled
Sustained 3T Write	: Enabled
Cache Rd+CPU Wt Pipeline	: Enabled
Read Around write	: Enabled
Cache Timing	: Fast
Video BIOS Cacheable	: Enabled
System BIOS Cacheable	: Disabled
Memory Hole At 15MB	: Disabled	ESC : Quit		Ç È Æ Å : Select Item
AGP	: Enabled	F1	: Help	PU/PD/+/- : Modify
Aperture Size	: 64M	F5	: Old Values	(Shift) F2 : Color
		F6	: Load BIOS Defaults
		F7	: Load Setup Defaults

Bank DRAM Timing

These fields defines the speed of the DRAM memory onboard. The options are Normal, Medium, Fast, Turbo, 70ns and 60ns. By default, these fields are set to 60ns.

DRAM Read Pipeline

When enabled, this field supports pipelining of DRAM reads The default setting is Enabled.

Sustained 3T Write

This field allows support for PBSRAM sustained 3T write. By default, this field is set Enabled.

Cache Rd+CPU Wt Pipeline

When enabled, this item allow pipelining of cache reads and CPU writes. The default setting is Enabled.

Read Around Write

DRAM optimization feature: If a memory read is addressed to a location whose latest write is being held in a buffer before being written to memory, the read is satisfied through the buffer contents, and the read is not sent to the DRAM. The default setting is Enabled.

40 AI5VG Pentium VP3 Baby AT Motherboard User’s Manual