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user manual Jumper Locations of the AI5VG, Hardware Settings
Models:
AI5VG
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Specifications
Install
BIOS Configuration
Wire Color
Reset Switch: Pins 9 and
BIOS Setup
Load BIOS Defaults
Typematic Delay Msec
Signal Name
Hardware Settings
Page 17
Image 17
Chapter 4 Hardware Settings
Figure 2: Jumper Locations of the AI5VG
AI5VG Pentium VP3 Baby AT Motherboard User’s Manual
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Contents
Pentium VP3 Baby AT Motherboard
AI5VG
User’s Manual
Page
Chapter 4 Hardware Settings
Contents
Chapter 6 BIOS Configuration
Chapter 1 Introduction
Checklist
•Introduction •Specifications
•Hardware Description •Hardware Settings
Main Processor
Chapter 2 Specifications
L2 Cache
Main Memory
CPU Temperature Sensor
BIOS
Onboard Bus Mastering EIDE
Windows 95 Shut-Down
Chapter 3 Hardware Description
Chapter 3 Hardware Description
Figure 1: Layout of the AI5VG Motherboard
3.2 L2 Cache Memory
3.1 Processor and CPU Voltage
3.3 Main Memory
Chapter 3 Hardware Description
Bank1
Bank0
Total Memory
SIMM1, SIMM2
Bank0 DIMM2
3.4 BIOS
Bank1 DIMM1
Total Memory
3.5 Onboard PCI EIDE
3.7 Onboard CPU Temperature Sensor
3.6 Onboard Multi-I/O
3. Power Management
3.9 DMA Channels
3.8 I/O Port Address Map
Address
Device Description
3.11 Accelerated Graphics Port AGP Slot
3.10 Interrupt Request Lines IRQ
Level
Function
Chapter 4 Hardware Settings
Chapter 4 Hardware Settings
Figure 2: Jumper Locations of the AI5VG
Mutiplier
Bus Clock
CPU FREQ
P55C = Pentium with MMX technology
Mutiplier
Bus Clock
CPU FREQ
Bus Clock
For Dual Voltage CPU
4.2 SW21-4:CPU Voltage Selector
Intel P55C, Cyrix 6x86L/MX, AMD K6
Bus Clock
3.3V
Function
4.3 JP5: Clear CMOS Selection
Function
Chapter 5 Installation
Chapter 5 Installation
Figure 3: Connector Location on the AI5VG
Figure 4: Orientation of the I/O Connector
5.1 I/O Connectors
5.2 J3: AT Power Supply Connector
Wire Color
5.4 J1, J4: AT Keyboard and PS/2 Mouse Connectors
5.3 J2: ATX Power Supply Connector
Signal Name
Signal Name
5.5 J7, J6: Serial Ports
5.6 J8: Floppy Drive Connector
Signal Name
Signal Name
J9: Primary IDE Connector
5.7 J9, J11: EIDE Connectors
Signal Name
Signal Name
5.9 J15: IrDA Connector
5.8 J10: Parallel Port Connector
5.10 J5: USB Connector
Signal Name
5.12 J14: CPU Fan Power Connector
5.11 J13 Wake on LAN Connector
5.13 J20 Front Bezel Connector
Pin # Signal Name
Signal Name
Speaker: Pins 1 -
Power LED and Keylock: Pins 11 -
Signal Name
J20 Pin #
Reset Switch: Pins 9 and
Signal Name
Chapter 6 BIOS Configuration
Cache Rd+CPU Wt Pipeline
IDE Primary/Secondary Master/Slave PIO
Press <DEL> to Enter Setup
6.1 BIOS Introduction
6.2 BIOS Setup
Chapter 7 LANDesk User Guide
STANDARD CMOS SETUP
Date
6.3 Standard CMOS Setup
Time
MODE for IDE HDD only : Auto
Primary HDDs / Secondary HDDs
CYLS
Drive A / Drive B
Floppy 3 Mode Support
Video
Halt On
CPU Internal Cache / External Cache
6.4 BIOS Features Setup
Virus Warning
Boot Sequence
Quick Power On Self Test
Boot Up Floppy Seek
Boot Up NumLock Status
Typematic Delay Msec
Typematic Rate Setting
Video BIOS Shadow
Typematic Rate Chars/Sec
Bank DRAM Timing
6.5 Chipset Features Setup
DRAM Read Pipeline
Sustained 3T Write
System BIOS Cacheable
Video BIOS Cacheable
Cache Timing
Memory Hole at 15MB Addr
Power Management
6.6 Power Management Setup
Doze Mode
HDD Power Down
Suspend Mode
PM Control by APM
Chapter 7 LANDesk User Guide
PM Events
PNP OS Installed
6.7 PNP/PCI Configuration
Reset Configuration Data
Resources Controlled by
PCI#2 Access #1 Retry
PCI Delay Transaction
CPU to PCI Write Buffer
PCI Dynamic Bursting
Chapter 7 LANDesk User Guide
PCI IDE IRQ Map To
Chapter 7 LANDesk User Guide
6.8 Load BIOS Defaults
6.9 Load Setup Defaults
IDE Prefetch Mode
6.10 Integrated Peripherals
IDE HDD Block Mode
OnChip Primary/Secondary PCI IDE
Onboard Parallel Mode
UART 2 Mode
IDE Primary/Secondary Master/Slave UDMA
Onboard FDD Controller
Chapter 7 LANDesk User Guide
6.11 Supervisor / User Password
Chapter 7 LANDesk User Guide
6.12 IDE HDD Auto Detection
6.13 HDD Low Level Format
Chapter 7 LANDesk User Guide
6.14 Save & Exit Setup
6.15 Exit Without Saving
