Intel Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion, 249323-003 MDIO Routing Port

LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion

Table 5. PHY Address Configuration Settings (Switch S1)

Jumper / Label	Description
S1-1 / ADD_0	Address <4:0> - Sets base address. Each port adds its port number (starting with 0)
	to this address to determine its PHY address.
S1-2 / ADD_1
	Switch “0” sets address bit to 0.
S1-3 / ADD_2	Switch “1” sets address bit to 10.
	Note: To make all ports accessible within the 0 - 31 PHY address range, DO NOT
S1-4 / ADD_3
	select a base address higher than 24.
	Port 0 = Base + 0
	Port 1 = Base + 1
	Port 2 = Base + 2
S1-5 / ADD_4	Port 3 = Base + 3
	Port 4 = Base + 4
	Port 5 = Base + 5
	Port 6 = Base + 6
	Port 7 = Base + 7

4.3Alternate MDIO Routing Configuration

The MDIO and MDC signals may be routed either through the 40-pin connector for MII Port 0 (the standard configuration) or through an RJ-11 connector (J2), as shown in Table 6. In either configuration, the MII registers can be accessed for each port by setting the correct PHY address. Refer to the LXT9785/9785E Data Sheet for specific register definitions and functions. The standard configuration is to route MDIO through the Port 0 MII connector to the SmartBits Test Box by setting the pins for JP1 and JP2 to 2 & 3.

Note: MDIO sectionalization is not supported on this demo board.

Table 6. MDIO Routing (Port 0)

Desired Configuration	Jumper	Setting	Description
	JP2	Jumper	Routes MDC0 through Port 0 MII Connector.
		Pins 2 & 3
Route MDIO0 and MDC0
through MII	JP1	Jumper	Routes MDIO0 through Port 0 MII Connector.
		Pins 2 & 3
	JP2	Jumper	Routes MDC0 through RJ-11 Connector J2.
		Pins 1 & 2
Route MDIO0 and MDC0
through RJ-11	JP1	Jumper	Routes MDIO0 through RJ-11 Connector J2.
		Pins 1 & 2

Development Kit Manual 15

Document #: 249323

Revision #: 003

Rev. Date: January 24, 2002