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Intel 249323-003 Development Kit Manual, Mdint, Remove, Mode, FOR 3.3V SD, Interface, Fpga, Jtag

Models: 249323-003 Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion

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Page 20

Rev. Date: January 24, 2002

Document #: 249323

Revision #: 003

Rev. Date: January 24, 2002

20

Development Kit Manual

6

A

B

C

D

E

Figure5.Control

LXD9785PQFPDemo

14

REF_CLK_0

REF_CLK_0

U1I

VCCIO

VCCIO

R6

4.7K

14

REF_CLK_1

REF_CLK_1

AMDIX_EN

83

AMDIX_EN

S8

MDC0

63

MDC0

MDC1

24

177

MODESEL_0

1

12

MDC1

MODESEL_0

MDIO0

64

178

MODESEL_1

2

11

MDIO0

MODESEL_1

R14

R15

R25

R16

R17

R10

MDIO1

25

176

SECTION

3

10

MDIO1

SECTION

59

MDIX

4

9

JP1

VCCIO

MDIX

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

85

CFG_3

5

8

CFG_3

86

CFG_2

6

7

1

CFG_2

SD_2P5V

95

87

CFG_1

4

SD_2P5V

CFG_1

4

J2

MDIO0_FIX

TSLEW_0

94

2

S5

TxSLEW_0

TSLEW_1

93

SW DIP-6

IN

1

TxSLEW_1

MDIO0_1

8

1

PAUSE

50

VCCIO

R3

R4

R5

R7

R26

R8

R9

2

3

PAUSE

7

2

PWRDWN

174

3

PWRDWN

HEADER 3X1

6

3

MDDIS

84

173

R726

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4

MDDIS

G_FX/TP

5

4

TFIFO

172

5

JP2

TFIFO

SECTION

RJ11

1

SW DIP-4

VCCIO

TP1

TP2

Board

HEADER 3X1

TDI

167

TDI

MDC0_FIX

1 1

2

TRST

171

TRST

GND

GND

D1

LED RD

170

TCK

MDC0_1

MDINT0

TCK

R12

220

67

169

TMS

3

MDINT0

TMS

VCCIO

R13

220

MDINT1

26

168

TDO

MDINT1

TDO

D93 LED RD

MDINT

REF_CLK_1

6

REFCLK1

ADD_3

89

ADD_3

4

S1

7

with

ADD_0

92

ADD_0

1

10

91

ADD_1

2

9

ADD_1

REF_CLK_0

44

90

ADD_2

3

8

VCCIO

REFCLK0

ADD_2

JP4

nRESET

175

RESET

ADD_4

88

ADD_4

5

6

FPGA

MDIO1_1

2

1

1

TP5

SW DIP-5

S4

D2

R23

LXT9785_SS/SMII

R18

R19

R20

R21

R22

3

J3

MDIO1_FIX

10K

3

2

VCCIO

LL4148

4.7K

4.7K

4.7K

4.7K

4.7K

1

1

U2A

U2B

IN

2

3

3

1

2

3

4

JP19

JP20

for

5

JP5

SW-NO

3

HEADER 3X1

4

R11

100

R24

6

74HC14

74HC14

GND

4.7K

JTAG

PORT

SS-

1

GND

+

C1

JP3

RJ11

MDC1_FIX

10uF

TRST

2

1

2

GND

GND

TCK

3

4

MDC1_1

TMS

SMII

3

5

6

GND

TDO

TDI

U1L

7

8

HEADER 3X1

GND

HEADER 4X2

(Fiber)-to

VCCIO

TX_CLK0

32

TX_CLK0(SS)

RX_CLK0(SS)

60

R558

45.3

RX_CLK0

TX_SYNC0

35

58

R559

45.3

RX_SYNC0

TXSYNC0(SS)

RX_SYNC0(SS)

MDIO0_1

MDIO0_1 4

VCC_PECL

2X4

MDIO1_1

MDIO1_1 6

REMOVE

JP12

TX_CLK1

201

TX_CLK1(SS)

RX_SYNC1(SS)

17

R568

30.1 1%RX_SYNC1

D155

TX_SYNC1

204

21

R569

30.1 1%RX_CLK1

JP12

SD_2P5V

MODE

TXSYNC1(SS)

RX_CLK1(SS)

MDC0_FIX

MDC0_FIX 17

FOR 3.3V SD

LED

MDIO0_FIX

MDIO0_FIX 17

2

U2C

2

INTERFACE

MDC1_FIX

MDC1_FIX 18

-MII

R725

5

6

R610

220

MDIO1_FIX

MDIO1_FIX 18

4.7K

LXT9785_SS/SMII

17

MDIO0

MDIO0

SECTION

74HC14

1

Conversion

U2D

RX_CLK

RX_CLK 13,16

9

8

R611

220

RX_SYNC

RX_SYNC

13,16

GND

1X8

RX_CLK1

RX_CLK1 13,16

4

MDC0_1

MDC0_1

74HC14

D156

RX_CLK0

RX_SYNC1

RX_SYNC1

13,16

6

MDC1_1

MDC1_1

MODE

LED

nRESET

nRESET 13

JP15

2

RX_CLK

SECTION

SECTION 14

17

MDC0

MDC0

GND

3

HEADER 3X1

18

MDC1

MDC1

RX_CLK1

18

MDIO1

MDIO1

U2E

U2F

RX_SYNC0

1

11

10

13

12

1

13,16

TX_CLK0

TX_CLK0

1

13,16 TX_SYNC0

TX_SYNC0

74HC14

74HC14

JP16

2

RX_SYNC

Title

13,16 TX_CLK1

TX_CLK1

3

HEADER 3X1

LXD9785 SS/SMII MII FX DV BOARD

13,16 TX_SYNC1

TX_SYNC1

RX_SYNC1

GND

Size

Document Number

Rev

B

CONTROL

A2

Date:

Wednesday, February 21, 2001

Sheet

3

of

18

A

B

C

D

E

Image 20

Intel 249323-003 Development Kit Manual, Mdint, Remove, Mode, FOR 3.3V SD, Interface, Rev. Date January, Fpga, Jtag, Port

Contents

January Development Kit ManualLXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion Copyright Intel Corporation Document # Revision # Rev. Date JanuaryContents ContentsFigures Tables ContentsRevision History ContentsDate RevisionPage 1.1 Features 1.0 General DescriptionLXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion Development Kit ManualFigure 1. LXD9785 PQFP MII Demo Board LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII ConversionDevelopment Kit Manual Document # 249323 Revision # 003 Rev. Date January2.3 Fiber Register Configuration 2.0 Introduction2.1 Overview 2.2 Equipment Requirements2.4 Typical Setup Figure 2. Typical Test SetupSmartBits Demo BoardFigure 3. LXD9785/9785E SS-SMII Fiber Demo Board LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII ConversionDevelopment Kit Manual Document # Revision # Rev. Date January 24LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion 3.0 Quick-Start ChecklistTable 1. Quick-Start Jumper Settings Table 2. Quick-Start Switch Settings Switch / LabelSetting Configuration4.0 Optional Configurations 4.1 Global Operating Configurations4.2 MII Address Configurations Table 3. Global Configuration Settings Switch S54.3 Alternate MDIO Routing Configuration Table 5. PHY Address Configuration Settings Switch S1Table 6. MDIO Routing Port LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion4.4 JTAG Test Signals Table 7. JTAG Test Signal Descriptions4.5 Extended Temperature Operation with the LXT9785HE LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII ConversionTable 8. Direct Drive LED Configuration Settings Register 5.0 LEDs5.1 Direct Drive LEDs LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII ConversionLXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion Table 9. LED Pulse Stretch Settings Register5.2 Inter Frame Status LEDs 6.0 Board Schematics Figure 4. LXD9785 PQFP MII Demo Board Power Fiber Board Revision A2LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion Development Kit ManualDevelopment Kit Manual MDINTREMOVE MODEFigure 6. MII Ports 0 and LXD9785PQFP Demo Board with FPGA for SS-SMIIDevelopment Kit Manual Rev. Date JanuaryFiber-to LXD9785 SS/SMII MII FX DV BOARDFigure 8. MII Ports 4 and Development Kit ManualLXD9785 PQFPDevelopment Kit Manual Rev. Date JanuaryLXD9785 SS/SMII MII FX DV BOARD Figure 9.MIIPorts6andFigure 10. Fiber Ports 0 and LXD9785 PQFPDevelopment Kit Manual Demo Board with FPGA for SS-SMIIFPGA for SS-SMII Fiber-to Kit ManualConversion Date JanuaryFigure 12. Fiber Ports 4 and Development Kit ManualLXD9785 PQFP Demo Board with FPGA for SS-SMIIFigure 13. Fiber Ports 6 and LXD9785 PQFP Demo Board withDevelopment Kit Manual FPGA for SS-SMII Fiber-toDevelopment Kit Manual BoardSMII withFigure 15. SS-SMII to MII ALTERA LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII ConversionDevelopment Kit Manual Document # 249323 Revision # 003 Rev. Date JanuaryFigure 16. Clock Distribution Development Kit ManualLXD9785 PQFP Demo Board with FPGA for SS-SMIIFigure 17. Inter-Frame Status LEDsFPGA for SS-SMII Fiber-toPQFP Demo Board with FPGA for SS-SMII Development Kit ManualLXD9785 Fiber-toFigure 19. MDIO0 and MDC0 Fix LXD9785 PQFP Demo Board with FPGAINSTALL R614 Development Kit ManualFigure 20. MDIO1 and MDC1 FixLXD9785 PQFP7.0 Bill of Materials Table 10. LXD9785 Bill of Materials Fiber - SS-SMIILXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion Development Kit ManualTable 10. LXD9785 Bill of Materials Fiber - SS-SMII Continued LXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII ConversionDevelopment Kit Manual Reference DesignatorLXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion Table 10. LXD9785 Bill of Materials Fiber - SS-SMII ContinuedDevelopment Kit Manual Reference DesignatorLXD9785 PQFP Demo Board with FPGA for SS-SMII Fiber-to-MII Conversion Table 10. LXD9785 Bill of Materials Fiber - SS-SMII ContinuedDevelopment Kit Manual Reference Designator