User’s Manual
3.11.38.2System
CLK | Clock provides timing for all transactions on PCI and is an input to every PCI device. |
| All other PCI signals, except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled |
| on the rising edge of CLK and all other timing parameters are defined with respect to |
| this edge. PCI operates up to 33 MHz or 66 MHz and, in general, the minimum |
| frequency is DC (0 Hz). |
RST# | Reset is used to bring |
| state. What effect RST# has on a device beyond the PCI sequencer is beyond the |
| scope of this specification, except for reset states of required PCI configuration |
| registers. Anytime RST# is asserted, all PCI output signals must be driven to their |
| benign state. In general, this means they must be asynchronously |
| (open drain) is floated. REQ# and GNT# must both be |
| driven low or high during reset). To prevent AD, C/BE#, and PAR signals from |
| floating during reset, the central resource may drive these lines during reset (bus |
| parking) but only to a logic low |
| asynchronous to CLK when asserted or deasserted. Although asynchronous, |
| deassertion is guaranteed to be a clean, |
| accesses, only devices that are required to boot the system will respond after reset. |