English
POST Error Code | ||||
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| POST (hex) |
| Description | |
CFh |
| Test CMOS R/W functionality. |
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C0h |
| Early chipset initialization: |
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C1h |
| 1. Detect memory |
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| 2. PEG slots |
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C3h |
| Expand compressed BIOS code to DRAM |
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C5h |
| Call chipset hook to copy BIOS back to E000 & F000 shadow RAM. |
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0h1 |
| Expand the Xgroup codes locating in physical address 1000:0 |
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03h |
| Initial Superio_Early_Init switch. |
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05h |
| 1. Blank out screen |
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| 2. Clear CMOS error flag |
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07h |
| 1. Clear 8042 interface |
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| 2. Initialize 8042 |
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08h |
| 1. | Test special keyboard controller for Winbond 977 series Super |
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| I/O chips. |
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| 2. Enable keyboard interface. |
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0Ah |
| 1. | Disable PS/2 mouse interface (optional). |
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| 2. Auto detect ports for keyboard & mouse followed by a port & |
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| interface swap (optional). |
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| 3. Reset keyboard for Winbond 977 series Super I/O chips. |
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0Eh |
| Test F000h segment shadow to see whether it is |
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| test fails, keep beeping the speaker. |
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10h |
| Auto detect flash type to load appropriate flash R/W codes into the |
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| run time area in F000 for ESCD & DMI support. |
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12h |
| Use walking 1’s algorithm to check out interface in CMOS |
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| circuitry. Also set |
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14h |
| Program chipset default values into chipset. Chipset default values are |
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| MODBINable by OEM customers. |
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16h |
| Initial Early_Init_Onboard_Generator switch. |
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18h |
| Detect CPU information including brand, SMI type (Cyrix or Intel) and CPU |
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| level (586 or 686). |
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1Bh |
| Initial interrupts vector table. If no special specified, all H/W interrupts are |
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| directed to SPURIOUS_INT_HDLR & S/W interrupts to |
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| SPURIOUS_soft_HDLR. |
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