Intel MFS2600KIB 3.2Processor Functions Overview

Intel® Compute Module MFS2600KI TPS			Functional Architecture
	Error	Severity	System Action
	Processor Intel® QuickPath	Fatal	The BIOS detects the QPI link frequencies and responds as follows:
	Interconnect link frequencies
			 Adjusts all QPI interconnect link frequencies to highest common
	not identical
			frequency.
			 No error is generated – this is not an error condition.
			 Continues to boot the system successfully.
			If the link frequencies for all QPI links cannot be adjusted to be the
			same, then this is an error, and the BIOS responds as follows:
			 Logs the POST Error Code into the SEL.
			 Alerts the BMC to set the System Status LED to steady Amber.
			 Displays “0195: Processor Intel® QPI link frequencies unable
			to synchronize” message in the Error Manager.
			 Does not disable the processor.
			Takes Fatal Error action (see above) and will not boot until the fault
			condition is remedied.

3.2Processor Functions Overview

With the release of the Intel® Xeon® processor E5-2600 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; two Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 40 lanes of Gen 3 PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* Gen 2 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space.

The following sections will provide an overview of the key processor features and functions that help to define the architecture, performance and supported functionality of the server board. For more comprehensive processor specific information, refer to the Intel® Xeon® processor E5- 2600 product family documents listed in the Reference Document list in Chapter 1.

Processor Core Features:

Up to 8 execution cores

Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket

46-bit physical addressing and 48-bit virtual addressing

1 GB large page support for server applications

A 32-KB instruction and 32-KB data first-level cache (L1) for each core

A 256-KB shared instruction/data mid-level (L2) cache for each core

Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores

Supported Technologies:

Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology for Directed I/O (Intel® VT-d)

Revision 1.0	9
	Intel order number: G51989-002