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Intel MFS2600KIB 3.7Network Interface Controller (NIC), 3.6.3.2Integrated BMC Embedded LAN Channel, 3.6.3.1Remote Keyboard, Video, Mouse, and Storage (KVMS) Support

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Intel® Compute Module MFS2600KI TPS

Functional Architecture

Interrupt controller

Multiple SPI flash interfaces

NAND/Memory interface

Sixteen mailbox registers for communication between the BMC and host

LPC ROM interface

BMC watchdog timer capability

SD/MMC card controller with DMA support

LED support with programmable blink rate controls on GPIOs

Port 80h snooping capability

Secondary Service Processor (SSP), which provides the HW capability of off-loading time critical processing tasks from the main ARM core.

3.6.3.1Remote Keyboard, Video, Mouse, and Storage (KVMS) Support

USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and floppy

USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse

Hardware Based Video Compression and Redirection Logic

Supports both text and Graphics redirection

Hardware assisted Video redirection using the Frame Processing Engine

Direct interface to the Integrated Graphics Controller registers and Frame buffer

Hardware-based encryption engine

3.6.3.2Integrated BMC Embedded LAN Channel

The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These interfaces are not shared with the host system. At any time, only one dedicated interface may be enabled for management traffic. The default active interface is the NIC 1 port.

3.7Network Interface Controller (NIC)

Network interface support is provided from the on-board Intel® I350 NIC, which is a single, compact component with two fully integrated GbE Media Access Control (MAC) and Physical Layer (PHY) ports. The on-board Intel® I350 NIC provides the Compute Module with support for dual LAN ports designed for 1000 Mbps operation.

The Intel® I350 device provides two standard IEEE 802.3 Ethernet interface through its SERDES interfaces. Each network interface controller (NIC) drives two LEDs (1 per port) located on the front panel. The LED indicates transmit/receive activity when blinking.

Table 14. NIC LED BEHAVIOR

	LED Color	LED State	NIC State
	Green	On	Link

		Blinking	Transmit / Receive activity
		Blinking	Transmit / Receive activity

Revision 1.0	25
	Intel order number: G51989-002

Contents

Revision June Enterprise Platforms and Services Division Revision History Disclaimers Table of Contents Introduction Product Overview Functional Architecture Page List of Figures List of Tables < This page intentionally left blank 1.Introduction 1.1Chapter Outline 2.Product Overview 2.1Intel® Compute Module MFS2600KI Feature Set 2.2Compute Module Layout 2.2.1Connector and Component Locations 2.2.3External I/O Connector Locations 3.Functional Architecture 3.1Intel® Xeon® processor 3.1.1Processor Support 3.1.1.1Processor Socket Assembly 3.1.1.2Processor Population Rules Note: 3.1.2Processor Initialization Error Summary Table 2. Mixed Processor Configurations 3.2Processor Functions Overview 3.2.1Intel® QuickPath Interconnect 3.2.2Intel® Hyper-ThreadingTechnology 3.3Processor Integrated I/O Module (IIO) 3.3.1PCI Express Interfaces 3.3.2DMI2 Interface to the PCH 3.3.3Integrated IOAPIC 3.3.4Intel® QuickData Technology 3.4Memory Subsystem 3.4.1Integrated Memory Controller (IMC) and Memory Subsystem 3.4.1.1Intel® Compute Module MFS2600KI Supported Memory Table 4. UDIMM Support Guidelines (Preliminary. Subject to Change) Table 5. RDIMM Support Guidelines (Preliminary. Subject to Change) Table 6. LRDIMM Support Guidelines (Preliminary. Subject to Change) 3.4.2Publishing Compute Module Memory 3.4.3Memory Map and Population Rules Page Page 3.4.3.1Memory Subsystem Nomenclature 3.4.4Memory RAS 3.5Intel® C602-JChipset Overvew 3.5.1Digital Media Interface (DMI) 3.5.2PCI Express* Interface 3.5.3Serial ATA (SATA) Controller 3.5.4Low Pin Count (LPC) Interface 3.5.5Serial Peripheral Interface (SPI) 3.6Integrated Baseboard Management Controller Overview 3.6.1Super I/O Controller 3.6.2Graphics Controller and Video Support 3.6.3Baseboard Management Controller 3.7Network Interface Controller (NIC) 3.8Intel® Virtualization Technology for Directed I/O (Intel® VT-d) 4.System Security 4.1BIOS Password Protection 4.2Trusted Platform Module (TPM) Support 4.2.1TPM security BIOS 4.2.2Physical Presence 4.2.3TPM Security Setup Options 4.3Intel® Trusted Execution Technology 5.Connector/Header Locations and Pin-outs 5.1Board Connector Information 5.2Power Connectors 5.3I/O Connector Pin-outDefinition 5.3.1VGA Connector 5.3.2I/O Mezzanine Card Connector Table 18. 120-pinI/O Mezzanine Card Connector Pin-out Table 19. 120-pinI/O Mezzanine Card Connector Signal Definitions Page 5.3.3Midplane Signal Connector 5.3.4Serial Port Connector 5.3.5USB 2.0 Connectors 5.3.6Low Profile eUSB SSD Support 6.Jumper Block Settings 6.1CMOS Clear and Password Clear Usage Procedure 6.2Integrated BMC Force Update Procedure 6.3Integrated BMC Initialization 6.4ME Force Update Jumper 6.5BIOS Recovery Jumper 7.Product Regulatory Requirements 7.1Product Regulatory Requirements 7.2Product Regulatory Compliance and Safety Markings 7.3Product Environmental/Ecology Requirements Appendix A: Integration and Usage Tips Appendix B: POST Code Diagnostic LED Decoder Table 27. POST Progress Codes POST Memory Initialization MRC Diagnostic Codes Page Page Appendix C: POST Error Code Page Page Page Page POST Error Beep Code Appendix D: Supported Intel® Modular Server System Glossary Glossary Page Reference Documents