Intel MFS2600KIB 59

Appendix C: POST Error Code		Intel® Compute Module MFS2600KI TPS

Error Code		Error Message	Response
8539	DIMM_I2 failed test/initialization		Major

853A	DIMM_I3 failed test/initialization		Major

853B	DIMM_J1 failed test/initialization		Major

853C	DIMM_J2 failed test/initialization		Major

853D	DIMM_J3 failed test/initialization		Major

853E	DIMM_K1 failed test/initialization		Major

853F	DIMM_K2 failed test/initialization		Major
(Go to
85C0)

8540	DIMM_A1 disabled		Major

8541	DIMM_A2 disabled		Major

8542	DIMM_A3 disabled		Major

8543	DIMM_B1 disabled		Major

8544	DIMM_B2 disabled		Major

8545	DIMM_B3 disabled		Major

8546	DIMM_C1 disabled		Major

8547	DIMM_C2 disabled		Major

8548	DIMM_C3 disabled		Major

8549	DIMM_D1 disabled		Major

854A	DIMM_D2 disabled		Major

854B	DIMM_D3 disabled		Major

854C	DIMM_E1 disabled		Major

854D	DIMM_E2 disabled		Major

854E	DIMM_E3 disabled		Major

854F	DIMM_F1 disabled		Major

8550	DIMM_F2 disabled		Major

8551	DIMM_F3 disabled		Major

8552	DIMM_G1 disabled		Major

8553	DIMM_G2 disabled		Major

8554	DIMM_G3 disabled		Major

8555	DIMM_H1 disabled		Major

8556	DIMM_H2 disabled		Major

8557	DIMM_H3 disabled		Major

8558	DIMM_I1 disabled		Major

8559	DIMM_I2 disabled		Major

855A	DIMM_I3 disabled		Major

855B	DIMM_J1 disabled		Major

855C	DIMM_J2 disabled		Major

855D	DIMM_J3 disabled		Major

855E	DIMM_K1 disabled		Major

855F	DIMM_K2 disabled		Major
(Go to
85D0)

8560	DIMM_A1 encountered a Serial Presence Detection (SPD) failure		Major

8561	DIMM_A2 encountered a Serial Presence Detection (SPD) failure		Major

8562	DIMM_A3 encountered a Serial Presence Detection (SPD) failure		Major

8563	DIMM_B1 encountered a Serial Presence Detection (SPD) failure		Major

52	Intel Confidential	Revision 1.0
	Intel order number: G51989-002

Contents

Revision June Enterprise Platforms and Services Division Revision History Disclaimers Table of Contents Introduction Product Overview Functional Architecture Page List of Figures List of Tables < This page intentionally left blank 1.Introduction 1.1Chapter Outline 2.Product Overview 2.1Intel® Compute Module MFS2600KI Feature Set 2.2Compute Module Layout 2.2.1Connector and Component Locations 2.2.3External I/O Connector Locations 3.Functional Architecture 3.1Intel® Xeon® processor 3.1.1Processor Support 3.1.1.1Processor Socket Assembly 3.1.1.2Processor Population Rules Note: 3.1.2Processor Initialization Error Summary Table 2. Mixed Processor Configurations 3.2Processor Functions Overview 3.2.1Intel® QuickPath Interconnect 3.2.2Intel® Hyper-ThreadingTechnology 3.3Processor Integrated I/O Module (IIO) 3.3.1PCI Express Interfaces 3.3.2DMI2 Interface to the PCH 3.3.3Integrated IOAPIC 3.3.4Intel® QuickData Technology 3.4Memory Subsystem 3.4.1Integrated Memory Controller (IMC) and Memory Subsystem 3.4.1.1Intel® Compute Module MFS2600KI Supported Memory Table 4. UDIMM Support Guidelines (Preliminary. Subject to Change) Table 5. RDIMM Support Guidelines (Preliminary. Subject to Change) Table 6. LRDIMM Support Guidelines (Preliminary. Subject to Change) 3.4.2Publishing Compute Module Memory 3.4.3Memory Map and Population Rules Page Page 3.4.3.1Memory Subsystem Nomenclature 3.4.4Memory RAS 3.5Intel® C602-JChipset Overvew 3.5.1Digital Media Interface (DMI) 3.5.2PCI Express* Interface 3.5.3Serial ATA (SATA) Controller 3.5.4Low Pin Count (LPC) Interface 3.5.5Serial Peripheral Interface (SPI) 3.6Integrated Baseboard Management Controller Overview 3.6.1Super I/O Controller 3.6.2Graphics Controller and Video Support 3.6.3Baseboard Management Controller 3.7Network Interface Controller (NIC) 3.8Intel® Virtualization Technology for Directed I/O (Intel® VT-d) 4.System Security 4.1BIOS Password Protection 4.2Trusted Platform Module (TPM) Support 4.2.1TPM security BIOS 4.2.2Physical Presence 4.2.3TPM Security Setup Options 4.3Intel® Trusted Execution Technology 5.Connector/Header Locations and Pin-outs 5.1Board Connector Information 5.2Power Connectors 5.3I/O Connector Pin-outDefinition 5.3.1VGA Connector 5.3.2I/O Mezzanine Card Connector Table 18. 120-pinI/O Mezzanine Card Connector Pin-out Table 19. 120-pinI/O Mezzanine Card Connector Signal Definitions Page 5.3.3Midplane Signal Connector 5.3.4Serial Port Connector 5.3.5USB 2.0 Connectors 5.3.6Low Profile eUSB SSD Support 6.Jumper Block Settings 6.1CMOS Clear and Password Clear Usage Procedure 6.2Integrated BMC Force Update Procedure 6.3Integrated BMC Initialization 6.4ME Force Update Jumper 6.5BIOS Recovery Jumper 7.Product Regulatory Requirements 7.1Product Regulatory Requirements 7.2Product Regulatory Compliance and Safety Markings 7.3Product Environmental/Ecology Requirements Appendix A: Integration and Usage Tips Appendix B: POST Code Diagnostic LED Decoder Table 27. POST Progress Codes POST Memory Initialization MRC Diagnostic Codes Page Page Appendix C: POST Error Code Page Page Page Page POST Error Beep Code Appendix D: Supported Intel® Modular Server System Glossary Glossary Page Reference Documents