Appendix B: POST Code Diagnostic LED Decoder | Intel® Compute Module MFS2600KI TPS |
The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step.
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| Table 28. MRC Progress Codes | ||||
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| Diagnostic LED Decoder |
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| 1 = LED On, 0 = LED Off |
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Checkpoint |
| Upper Nibble |
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| Lower Nibble |
| Description | ||
| MSB |
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| LSB | |
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| 8h | 4h | 2h | 1h | 8h | 4h | 2h | 1h |
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#7 | #6 | #5 | #4 | #3 | #2 | #1 | #0 |
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MRC Progress Codes |
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B0h | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | Detect DIMM population |
B1h | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | Set DDR3 frequency |
B2h | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Gather remaining SPD data |
B3h | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | Program registers on the memory controller level |
B4h | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | Evaluate RAS modes and save rank information |
B5h | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | Program registers on the channel level |
B6h | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | Perform the JEDEC defined initialization sequence |
B7h | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | Train DDR3 ranks |
B8h | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Initialize CLTT/OLTT |
B9h | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | Hardware memory test and init |
BAh | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | Execute software memory init |
BBh | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | Program memory map and interleaving |
BCh | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Program RAS configuration |
BFh | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | MRC is done |
Memory Initialization at the beginning of POST includes multiple functions, including: discovery, channel training, validation that the DIMM population is acceptable and functional, initialization of the IMC and other hardware settings, and initialization of applicable RAS configurations.
When a major memory initialization error occurs and prevents the system from booting with data integrity, a beep code is generated, the MRC will display a fatal error code on the diagnostic LEDs, and a system halt command is executed. Fatal MRC error halts do NOT change the state of the System Status LED, and they do NOT get logged as SEL events. The following table lists all MRC fatal errors that are displayed to the Diagnostic LEDs.
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| Table 29. MRC Fatal Error Codes | ||||
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| Diagnostic LED Decoder |
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| 1 = LED On, 0 = LED Off |
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Checkpoint |
| Upper Nibble |
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| Description | |
| MSB |
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| LSB | |
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| 8h | 4h | 2h | 1h | 8h | 4h | 2h | 1h |
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LED | #7 | #6 | #5 | #4 | #3 | #2 | #1 | #0 |
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MRC Fatal Error Codes |
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E8h | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | No usable memory error |
E9h | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | Memory is locked by Intel® Trusted Execuiton Technology and is |
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EAh | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | DDR3 channel training error |
48 | Intel Confidential | Revision 1.0 |
| Intel order number: |
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