Intel SDS2 manual Memory Subsystem, Processor Voltage Regulator Module VRM, Memory Configuration

Processor and Chipset Intel® Server Board SDS2

3.1.1Processor Voltage Regulator Module (VRM)

The SDS2 Server Board has dual, on board, RM circuitry to support the two processors. The circuit is compliant with the VRM8.5 specification and provides a maximum of 60A, which will support the currently available processors and future releases of the Pentium III processors.

The board hardware and the BMC read the processor VID (Voltage Identification) bits for each processor before turning on the power to the processors (VRMs). If the VIDs of the two processors are not identical, then the BMC will not turn on the VRMs and a beep code is generated. Table 30. BMC Beep Codes lists all of the error codes.

3.2Memory Subsystem

The SDS2 Server Board supports up to six DIMM sockets for a maximum memory capacity of 6 GB using 1 GB DIMMs . The DIMM organization is x72, which includes 8 ECC check bits. ECC from the DIMMs is passed through to the processor front side bus.

The SDRAM interface runs at the same frequency as the processor bus. The memory controller supports 2-way interleaved SDRAM, memory scrubbing, single-bit error correction, and multiple- bit error detection. Memory can be implemented with either single-sided (one row) or double- sided (two row) DIMMs.

∙Only registered PC-133 compliant memory is supported

∙Support is 2-way interleaved SDRAM and requires two DIMMs to be installed per bank.

∙ECC single-bit error correction and multiple-bit error detection

∙Maximum memory capacity of 6 GB

∙Minimum memory capacity of 128 MB

Note: Memory interleaving is a way to increase memory performance by allowing the system to access multiple memory modules simultaneously, rather than sequentially, in a similar fashion to Hard Drive striping. Interleaving can only take place between identical memory modules.

3.2.1Memory Configuration

Memory configuration requirements are as follow:

∙PC-133 SDRAM Registered DIMM modules

∙DIMM organization: x72 ECC

∙Pin count: 168

∙SDRAM Supported: 64 Mb, 128 Mb, 256 Mb

∙DIMM capacity: 64 MB, 128 MB, 256 MB, 512 MB, 1 GB

∙Serial PD: JEDEC Rev 2.0

∙Voltage Options: 3.3 V (VDD/VDDQ)

∙Interface: LVTTL

∙DIMMs must be populated in pairs for a x144 wide memory data path

∙Any or all memory banks may be populated

6	Revision 1.2
Order Number:	A85874-002