UPI-C42/UPI-L42

Table1. Pin Description

DIP PLCC QFP
Symbol Pin Pin Pin Type Nameand Function
No. No. No.
TEST0, 1 2 18 I TESTINPUTS: Input pins which can be directly tested using conditional
branchinstructions.
TEST1 39 43 16
FREQUENCYREFERENCE: TEST 1 (T1) functions as the event timer
input(under software control). TEST 0 (T0) is a multi-function pin used
duringPROM programming and ROM/EPR OM verification, during Sync
Modeto reset the instruction state to S1 and synchronize the internal clock
toPH1.
XTAL1 2 3 19 O OUTPUT:Output from the oscillator amplifier.
XTAL2 3 4 20 I INPUT: Input to the oscillator amplifier and internal clock generator
circuits.
RESET 4 5 22 I RESET: Input used to reset status flip-flops, set the program counter to
zero,and force the UPI-C42 from the suspend power down mode.
RESETis also used during EPROM programming and verification.
SS 5 6 23 I SINGLESTEP: Single step input used in conjunction with the SYNC output
tostep the program through each instruction (EPROM). This should be tied
to a5Vwhen not used. This pin is also used to put the device in Sync
Modeby applying 12.5V to it.
CS 6 7 24 I CHIP SELECT: Chip select input used to select one UPI microcomputer
outof several connected to a common data bus.
EA 7 8 25 I EXTERNAL ACCESS: External access input which allows emulation,
testingand ROM/EPROM verification. This pin should be tied low if
unused.
RD 8 9 26 I READ: I/O read input which enables the master CPU to read data and
statuswords from the OUTPUT DATA BUS BUFFER or status register.
A091027ICOMMAND/DATASELECT: Address Input used by the master processor
toindicate whether byte transfer is data (A0e0, F1 is reset) or command
(A0e1,F1 is set). A0e0 during program and verify operations.
WR 10 11 28 I WRITE:I/Owrite input which enables the master CPU to write data and
commandwords to the UPI INPUT DATA BUS BUFFER.
SYNC 11 13 29 O OUTPUT CLOCK: Output signal which occurs once per UPI instruction
cycle.SYNC can be used as a strobe for external circuitry; it is also used to
synchronizesingle step operation.
D0–D7
(BUS)
12–19 14–21 30–37 I/O DATABUS: Three-state, bidirectional DATA BUS BUFFER lines used to
interfacethe UPI microcomputer to an 8-bit master system data bus.
P10–P17 27–34 30–33 2–10 I/O PORT 1: 8-bit, PORT 1 quasi-bidirectional I/O lines. P10 –P17access the
signaturerow and security bit.
35–38
2