Intel UPI-C42, UPI-L42

UPI-C42/UPI-L42

WAVEFORMS

READ OPERATIONÐDATA BUS BUFFER REGISTER

290414–22

WRITE OPERATIONÐDATA BUS BUFFER REGISTER

290414–23

CLOCK TIMING

290414–24

Contents

Main UPI-C42/UPI-L42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER UPI-C42/UPI-L42 Table1. Pin Description Table1. Pin Description (Continued) Figure4. Block Diagram UPI-C42/L42 PRODUCT SELECTION GUIDE THE INTEL 82C42 UPI-42 COMPATIBLE FEATURES UPI-C42 FEATURES Programmable Memory Size Increase Extended Memory Program Addressing (Beyond 2K) PROGRAM MEMORY BANK SWITCH INTERRUPT ROUTINES Hardware A20 Gate Support Suspend Mode Summary # # # # # NEW UPI-C42 INSTRUCTIONS New Instructions PROGRAMMING AND VERIFYING THE UPI-C42 Quick-Pulse Programming Algorithm Verify SECURITY BIT SECURITY BIT PROGRAMMING/ VERIFICATION Programming Verification SIGNATURE MODE SYNC MODE ACCESS CODE SYNC MODE TIMING DIAGRAMS APPLICATIONS ABSOLUTE MAXIMUM RATINGS* DC CHARACTERISTICS DC CHARACTERISTICS DC CHARACTERISTICSPROGRAMMING (UPI-C42 AND UPI-L42) Page AC CHARACTERISTICS AC CHARACTERISTICS AC CHARACTERISTICSPROGRAMMING (UPI-C42 AND UPI-L42) u Page Page WAVEFORMS COMBINATION PROGRAM/VERIFY MODE VERIFY MODE WAVEFORMS Table4. UPI Instruction Set Table4. UPI Instruction Set (Continued) REVISION SUMMARY -003: 1. Delete all references to standby power down mode. -001: 1. Added UPI-L42 references and specification.