UPI-C42/UPI-L42

Table4. UPI Instruction Set (Continued)

Mnemonic Description Bytes Cycles
CONTROL(Continued)
*SUSPEND InvokeSuspend Power- 1 2
downmode
NOP NoOperation 1 1
REGISTERS
INCRr Increment register 1 1
INC @Rr Incrementdata 1 1
memory
DECRr Decrement register 1 1
SUBROUTINE
CALLaddr Jumpto subroutine 2 2
RET Return 1 2
RETR Return and restore 1 2
status
FLAGS
CLRC Clear Carry 1 1
CPLC Complement Carry 1 1
CLRF0 ClearFlag 0 1 1
CPLF0 Complement Flag 0 1 1
CLRF1 ClearF1 Flag 1 1
CPLF1 Complement F1 Flag 1 1
Mnemonic Description Bytes Cycles
BRANCH
JMPaddr Jumpunconditional 2 2
JMPP @A Jump indirect 1 2
DJNZRr, addr Decrement register 2 2
andjump
JCaddr Jumpon Carry e12 2
JNCaddr Jumpon Carry e02 2
JZaddr Jumpon A Zero 2 2
JNZaddr Jump on A not Zero 2 2
JT0addr Jump on T0 e122
JNT0addr Jump on T0 e022
JT1addr Jump on T1 e122
JNT1addr Jump on T1 e022
JF0addr Jump on F0 Flag e12 2
JF1addr Jump on F1 Flag e12 2
JTFaddr Jump on Timer Flag 2 2
e1,Clear Flag
JNIBFaddr Jump on IBF Flag 2 2
e0
JOBFaddr Jumpon OBF Flag 2 2
e1
JBbaddr Jump on Accumula- 2 2
forBit
*UPI-C42/UPI-L42Only.
REVISION SUMMARY
The following has been changed since Revision

-003:

1. Delete all references to standby power down

mode.

The following has been changed since Revision

-002:

1. Added information on keyboard controller prod-

uct family.

2. Added IHI specification for the UPI-L42.

The following has been changed since Revision

-001:

1. Added UPI-L42 references and specification.

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