Intel UPI-C42, UPI-L42 Table4. UPI Instruction Set

UPI-C42/UPI-L42

Table4. UPI Instruction Set

Mnemonic Description Bytes Cycles

ACCUMULATOR

ADDA, Rr Add register to A 1 1

ADDA, @Rr Adddata memory 1 1

toA

ADDA, Ýdata Addimmediate to A 2 2

ADDCA, Rr Add register to A 1 1

withcarry

ADDCA, @Rr Adddata memory 1 1

toA with carry

ADDCA, Ýdata Add immediate 2 2

toA with carry

ANLA, Rr ANDregister to A 1 1

ANL,A @Rr AND data memory 1 1

toA

ANLA, Ýdata AND immediate to A 2 2

ORLA, Rr OR register to A 1 1

ORL,A, @Rr ORdata memory 1 1

toA

ORLA, Ýdata ORimmediate to A 2 2

XRLA, Rr Exclusive OR regis- 1 1

terto A

XRLA, @Rr Exclusive OR data 1 1

memoryto A

XRLA, Ýdata Exclusive OR imme- 2 2

diateto A

INCA IncrementA 1 1

DECA Decrement A 1 1

CLRA Clear A 1 1

CPLA Complement A 1 1

DAA Decimal Adjust A 1 1

SWAPA Swap nibbles of A 1 1

RLA Rotate A left 1 1

RLCA Rotate A left through 1 1

carry

RRA RotateA right 1 1

RRCA RotateA right 1 1

throughcarry

INPUT/OUTPUT

INA, Pp Input port to A 1 2

OUTLPp, A Output A to port 1 2

ANLPp, Ýdata AND immediate to 2 2

port

ORLPp, Ýdata ORimmediate to 2 2

port

INA, DBB Input DBB to A, 1 1

clearIBF

OUTDBB, A Output A to DBB, 1 1

setOBF

MOVSTS, A A4–A7toBits 4 –7 of 1 1

Status

MOVDA, Pp Input Expander 1 2

portto A

MOVDPp, A Output A to 1 2

Expanderport

ANLDPp, A AND A to Expander 1 2

port

ORLDPp, A ORA to Expander 1 2

port

Mnemonic Description Bytes Cycles

DATAMOVES

MOVA, Rr Move register to A 1 1

MOVA, @Rr Move data memory 1 1

toA

MOVA, Ýdata Move immediate to A 2 2

MOVRr, A Move A to register 1 1

MOV @Rr,A MoveA to data 1 1

memory

MOVRr, Ýdata Move immediate to 2 2

register

MOV @Rr, Move immediate to 2 2

Ýdata data memory

MOVA, PSW Move PSW to A 1 1

MOVPSW, A Move A to PSW 1 1

XCHA, Rr Exchange A and 1 1

register

XCHA, @Rr ExchangeA and 1 1

datamemory

XCHDA, @Rr Exchangedigitof A 1 1

andregister

MOVPA, @A Moveto A from 1 2

currentpage

MOVP3,A, @A Move to A from 1 2

page3

TIMER/COUNTER

MOVA, T ReadTimer/Counter 1 1

MOVT, A LoadTimer/Counter 1 1

STRTT Start Timer 1 1

STRTCNT Start Counter 1 1

STOPTCNT StopTimer/Counter 1 1

ENTCNTI Enable Timer/ 1 1

CounterInterrupt

DISTCNTI Disable Timer/ 1 1

CounterInterrupt

CONTROL

*ENA20 EnableA20 Logic 1 1

ENDMA EnableDMA Hand- 1 1

shakeLines

ENI EnableIBF Interrupt 1 1

DISI Diable IBF Inter- 1 1

rupt

ENFLAGS Enable Master 1 1

Interrupts

*SELPMB0 Select Program 1 1

memorybank 0

*SELPMB1 Select Program 1 1

memorybank 1

SELRB0 Select register 1 1

bank0

SELRB1 Select register 1 1

bank1

*UPI-C42/UPI-L42Only.

24

Contents

Main UPI-C42/UPI-L42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER UPI-C42/UPI-L42 Table1. Pin Description Table1. Pin Description (Continued) Figure4. Block Diagram UPI-C42/L42 PRODUCT SELECTION GUIDE THE INTEL 82C42 UPI-42 COMPATIBLE FEATURES UPI-C42 FEATURES Programmable Memory Size Increase Extended Memory Program Addressing (Beyond 2K) PROGRAM MEMORY BANK SWITCH INTERRUPT ROUTINES Hardware A20 Gate Support Suspend Mode Summary # # # # # NEW UPI-C42 INSTRUCTIONS New Instructions PROGRAMMING AND VERIFYING THE UPI-C42 Quick-Pulse Programming Algorithm Verify SECURITY BIT SECURITY BIT PROGRAMMING/ VERIFICATION Programming Verification SIGNATURE MODE SYNC MODE ACCESS CODE SYNC MODE TIMING DIAGRAMS APPLICATIONS ABSOLUTE MAXIMUM RATINGS* DC CHARACTERISTICS DC CHARACTERISTICS DC CHARACTERISTICSPROGRAMMING (UPI-C42 AND UPI-L42) Page AC CHARACTERISTICS AC CHARACTERISTICS AC CHARACTERISTICSPROGRAMMING (UPI-C42 AND UPI-L42) u Page Page WAVEFORMS COMBINATION PROGRAM/VERIFY MODE VERIFY MODE WAVEFORMS Table4. UPI Instruction Set Table4. UPI Instruction Set (Continued) REVISION SUMMARY -003: 1. Delete all references to standby power down mode. -001: 1. Added UPI-L42 references and specification.