NEC - page 230

230
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0000 TI2 input cycle 28 × TI2 input cycle TI2 input edge cycle
0001 TI2 input cycle 28 × TI2 input cycle TI2 input edge cycle
2 × 1/fX22 × 1/fX29 × 1/fX210 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (102.4 µ s) (204.8 µ s) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX210 × 1/fX211 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6 µ s) (204.8 µ s) (409.6 µ s) (800 ns) (1.6 µ s)
23 × 1/fX24 × 1/fX211 × 1/fX212 × 1/fX23 × 1/fX24 × 1/fX
(1.6 µ s) (3.2 µ s) (409.6 µ s) (819.2 µ s) (1.6 µ s) (3.2 µ s)
24 × 1/fX25 × 1/fX212 × 1/fX213 × 1/fX24 × 1/fX25 × 1/fX
(3.2 µ s) (6.4 µ s) (819.2 µ s) (1.64 ms) (3.2 µ s) (6.4 µ s)
25 × 1/fX26 × 1/fX213 × 1/fX214 × 1/fX25 × 1/fX26 × 1/fX
(6.4 µ s) (12.8 µ s) (1.64 ms) (3.28 ms) (6.4 µ s) (12.8 µ s)
26 × 1/fX27 × 1/fX214 × 1/fX215 × 1/fX26 × 1/fX27 × 1/fX
(12.8 µ s) (25.6 µ s) (3.28 ms) (6.55 ms) (12.8 µ s) (25.6 µ s)
27 × 1/fX28 × 1/fX215 × 1/fX216 × 1/fX27 × 1/fX28 × 1/fX
(25.6 µ s) (51.2 µ s) (6.55 ms) (13.1 ms) (25.6 µ s) (51.2 µ s)
28 × 1/fX29 × 1/fX216 × 1/fX217 × 1/fX28 × 1/fX29 × 1/fX
(51.2 µ s) (102.4 µ s) (13.1 ms) (26.2 ms) (51.2 µ s) (102.4 µ s)
29 × 1/fX210 × 1/fX217 × 1/fX218 × 1/fX29 × 1/fX210 × 1/fX
(102.4 µ s) (204.8 µ s) (26.2 ms) (52.4 ms) (102.4 µ s) (204.8 µ s)
211 × 1/fX212 × 1/fX219 × 1/fX220 × 1/fX211 × 1/fX212 × 1/fX
(409.6 µ s) (819.2 µ s) (104.9 ms) (209.7 ms) (409.6 µ s) (819.2 µ s)
Other than above Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. MCS : Bit 0 of oscillation mode selection register (OSMS)
3. TCL14 to TCL17 : Bits 4 to 7 of timer clock select register 1 (TCL1)
4. Values in parentheses when operated at fX = 5.0 MHz
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TCL17TCL16 TCL15 TCL14