470
CHAPTER 19 SERIAL INTERFACE CHANNEL 2
5-Bit Counter Source Clock Selection
TPS3 TPS2 TPS1 TPS0 n
MCS = 1 MCS = 0
0000fXX/210 fX/210 (4.9 kHz) fX/211 (2.4 kHz) 11
0101fXX fX(5.0 MHz) fX/2 (2.5 MHz) 1
0110fXX/2 fX/2 (2.5 MHz) fX/22(1.25 MHz) 2
0111fXX/22fX/22(1.25 MHz) fX/23(625 kHz) 3
1000fXX/23fX/23(625 kHz) fX/24(313 kHz) 4
1001fXX/24fX/24(313 kHz) fX/25(156 kHz) 5
1010fXX/25fX/25(156 kHz) fX/26(78.1 kHz) 6
1011fXX/26fX/26(78.1 kHz) fX/27(39.1 kHz) 7
1100fXX/27fX/27(39.1 kHz) fX/28(19.5 kHz) 8
1101fXX/28fX/28(19.5 kHz) fX/29(9.8 kHz) 9
1110fXX/29fX/29(9.8 kHz) fX/210 (4.9 kHz) 10
Other than above Setting prohibited
Caution When a Data is written to BRGC during a communication operation, baud rate generator
output is disrupted and communication cannot be performed normally. Therefore, data
must not be written to BRGC during a communication operation.
Remarks 1. fX: Main system clock oscillation frequency
2. fXX : Main system clock frequency (fX or fX/2)
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. n : Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
5. Figures in parentheses apply to operation with fX = 5.0 MHz.