NEC 26.2 Memory Size Switching Register (, PD78P058)

550
CHAPTER 26 µ PD78P054, 78P058
7
RAM2
Symbol
IMS
6
RAM1
5
RAM0
4
0
3
ROM3
2
ROM2
1
ROM1
0
ROM0
Address
FFF0H CFH
After
Reset R/W
R/W
1
Internal ROM Capacity selection
32 Kbytes
ROM3
0
ROM2
0
ROM1
0
ROM0
Setting prohibitedOther than above
Internal High-Speed RAM Capacity Selection RAM2 RAM1 RAM0
512 bytes010
Setting prohibitedOther than above
0
0
16 Kbytes
24 Kbytes
1
1
0
1
0
0
1024 bytes110
1 56 Kbytes110
1
1
40 Kbytes
48 Kbytes
0
1
1
0
0
0
1 60 Kbytes
111
26.2 Memory Size Switching Register ( µ PD78P058)
The µ PD78P058 allows users to define its internal ROM and high-speed RAM sizes using the memory size
switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal
ROM and high-speed RAM is possible. IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Figure 26-2. Memory Size Switching Register Format (
µ PD78P058)
The IMS settings to give the same memory map as mask ROM versions are shown in Table 26-4.
Table 26-4. Examples of Memory Size Switching Register Settings (
µ PD78P058)
Relevant Mask ROM Version IMS Setting
µ PD78052, 78052Y 44H
µ PD78053, 78053Y C6H
µ PD78054, 78054Y C8H
µ PD78055, 78055Y CAH
µ PD78056, 78056Y CCH
µ PD78058, 78058Y CFH