NEC - page 235

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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2)
are Used as 16-Bit Timer/Event Counter
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0000 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle
0001 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle
2 × 1/fX22 × 1/fX217 × 1/fX218 × 1/fX2 × 1/fX22 × 1/fX
(400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
22 × 1/fX23 × 1/fX218 × 1/fX219 × 1/fX22 × 1/fX23 × 1/fX
(800 ns) (1.6 µ s) (52.4 ms) (104.9 ms) (800 ns) (1.6 µ s)
23 × 1/fX24 × 1/fX219 × 1/fX220 × 1/fX23 × 1/fX24 × 1/fX
(1.6 µ s) (3.2 µ s) (104.9 ms) (209.7 ms) (1.6 µ s) (3.2 µ s)
24 × 1/fX25 × 1/fX220 × 1/fX221 × 1/fX24 × 1/fX25 × 1/fX
(3.2 µ s) (6.4 µ s) (209.7 ms) (419.4 ms) (3.2 µ s) (6.4 µ s)
25 × 1/fX26 × 1/fX221 × 1/fX222 × 1/fX25 × 1/fX26 × 1/fX
(6.4 µ s) (12.8 µ s) (419.4 ms) (838.9 ms) (6.4 µ s) (12.8 µ s)
26 × 1/fX27 × 1/fX222 × 1/fX223 × 1/fX26 × 1/fX27 × 1/fX
(12.8 µ s) (25.6 µ s) (838.9 ms) (1.7 s) (12.8 µ s) (25.6 µ s)
27 × 1/fX28 × 1/fX223 × 1/fX224 × 1/fX27 × 1/fX28 × 1/fX
(25.6 µ s) (51.2 µ s) (1.7 s) (3.4 s) (25.6 µ s) (51.2 µ s)
28 × 1/fX29 × 1/fX224 × 1/fX225 × 1/fX28 × 1/fX29 × 1/fX
(51.2 µ s) (102.4 µ s) (3.4 s) (6.7 s) (51.2 µ s) (102.4 µ s)
29 × 1/fX210 × 1/fX225 × 1/fX226 × 1/fX29 × 1/fX210 × 1/fX
(102.4 µ s) (204.8 µ s) (6.7 s) (13.4 s) (102.4 µ s) (204.8 µ s)
211 × 1/fX212 × 1/fX227 × 1/fX228 × 1/fX211 × 1/fX212 × 1/fX
(409.6 µ s) (819.2 µ s) (26.8 s) (53.7 s) (409.6 µ s) (819.2 µ s)
Other than above Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. MCS : Oscillation mode selection register (OSMS) bit 0
3. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register (TCL1)
4. Values in parentheses when operated at fX = 5.0 MHz.
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TCL13TCL12 TCL11 TCL10