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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054 Subseries)
Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1)
1 2 3 4 5 6 7 8 9SCK0 Pin
A7 A6 A5 A4 A3 A2 A1 A0 ACK BUSYSB0 (SB1) Pin
Program Processing
Serial Transmission INTCSI0
Generation
ACKD
Set
SCK0
Stop
Hardware Operation
WUP0ACKT
Set
Program Processing
CMDD
Set
INTCSI0
Generation
ACK
Output
Hardware Operation
CMDT
Set RELT
Set CMDT
Set Write
to SIO0 Interrupt Servicing
(Preparation for the Next Serial Transfer)
Master Device Processing (Transmitter)
Transfer Line
Slave Device Processing (Receiver)
CMDD
Clear CMDD
Set
RELD
Set
Serial Reception BUSY
Output
READY
(When SVA = SIO0)
Address
BUSY
Clear
BUSY
Clear