Main                
PD78054, 78054Y SUBSERIES
Users Manual            
Page
              NOTES FOR CMOS DEVICES
            Page
            Page
              Regional Information
NEC Electronics Hong Kong Ltd.                
  Device availability
  Ordering information                
  Product release schedule
              Major Revisions in This Edition
The mark    shows major revised points.            
Page
              PREFACE
            Page
              Chapter Organization: This manual divides the descriptions for the 
            Page
            Page
              Development Tool Documents (Users Manuals)
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              LIST OF FIGURES (1/8)
              LIST OF FIGURES (2/8)
              LIST OF FIGURES (3/8)
              LIST OF FIGURES (4/8)
              LIST OF FIGURES (5/8)
              LIST OF FIGURES (6/8)
              LIST OF FIGURES (7/8)
              LIST OF FIGURES (8/8)
              LIST OF TABLES (1/3)
              LIST OF TABLES (2/3)
              LIST OF TABLES (3/3)
            Page
              CHAPTER 1  GENERAL (
1.1  Features              
1.2  Applications
Caution The                 
1.3  Ordering Information
PD78P054GC is available in two packages.  For the package that can be supplied, consult NEC.              
1.4  Quality Grade
Cautions 1. The                 
PD78P054GC is available in two packages.  For the package that can be supplied, consult NEC. 2. The 
              1.5  Pin Configuration (Top View)
(1) Normal operating mode  80-pin plastic QFP (14                 
PD78P054, 78P058.
78056GK--BE9,                
PD78055GK--BE9,
              Pin Identifications
              (2) PROM programming mode 80-pin plastic QFP (14  14 mm, Resin thickness: 2.7 mm)
PD78P054GC-3B9                
PD78P054GC-8BTNote, 78P058GC-8BT 80-pin plastic TQFP (Fine pitch) (12  12 mm)
PD78P054GK-BE9                
PD78P054KK-T, 78P058KK-T
              1.6  78K/0 Series Expansion
The products in the 78K/0 Series are listed below.  The names in boxes are subseries names.                
Note Planned
              The following shows the major differences between subseries products.
Notes 1. 16-bit timer: 2 channels 10-bit timer: 1 channel 2. 10-bit timer: 1 channel              
1.7  Block Diagram
PD78P054, 78P058.              
1.8  Outline of Function
PD78P054 is the PROM version for the                 
PD78P058 is the PROM version for the 
Notes 1. The                 
PD78052, 78053, and 78054. 2. The 
              Notes 1. The 
PD78P054 is the PROM version for the                 
PD78P054 is under development.
PD78P058 is the PROM version for the                 
PD78052, 78053, 78054. 2. The 
              1.9  Differences between Standard Quality Grade Products and (A) Products
1.10  Mask Options              
CHAPTER 2  GENERAL (
2.1  Features              
2.2  Applications
2.3  Ordering Information                
2.4  Quality Grade
              2.5  Pin Configuration (Top View)
(1) Normal operating mode                
PD78P058Y.
PD78052YGC--8BT, 78053YGC--8BT, 78054YGC--8BT                
PD78055YGC--8BT, 78056YGC--8BT, 78058YGC--8BT, 78P058YGC-8BT
              Pin Identifications
              (2) PROM programming mode
PD78P058YGC-8BT                
PD78P058YKK-T
PD78054Y Subseries)              
2.6  78K/0 Series Expansion
The products in the 78K/0 Series are listed below.  The names in boxes are subseries names.                
Note Planned
              Major differences among Y subseries are tabulated below.
Remark The functions except serial interface are common with subseries without Y.              
2.7  Block Diagram
PD78P058.              
2.8  Outline of Function
              2.9  Mask Options
The mask ROM versions (                
PD78054Y subseries are shown in Table 2-1. Table 2-1.  Mask Options of Mask ROM Versions
              CHAPTER 3  PIN FUNCTION (
3.1  Pin Function List                
3.1.1  Normal operating mode pins (1) Port pins (1/3)
              (1) Port pins (2/3)
              (1) Port pins (3/3)
              (2) Pins other than port pins (1/2)
              (2) Pins other than port pins (2/2)
3.1.2  PROM programming mode pins (PROM versions only)              
3.2  Description of Pin Functions
            Page
            Page
            Page
            Page
            Page
            Page
              3.3  Input/output Circuits and Recommended Connection of Unused Pins
              Table 3-1.  Pin Input/Output Circuit Types (2/2)
              Figure 3-1.  Pin Input/Output Circuit of List (1/2)
              Figure 3-1.  Pin Input/Output Circuit of List (2/2)
              CHAPTER 4  PIN FUNCTION (
4.1  Pin Function List                
4.1.1  Normal operating mode pins (1) Port pins (1/3)
              (1) Port pins (2/3)
              (1) Port pins (3/3)
              (2) Pins other than port pins (1/2)
              (2) Pins other than port pins (2/2)
4.1.2  PROM programming mode pins (PROM versions only)              
4.2  Description of Pin Functions
            Page
            Page
            Page
            Page
            Page
            Page
              4.3  Input/output Circuits and Recommended Connection of Unused Pins
              Table 4-1.  Pin Input/Output Circuit Types (2/2)
              Figure 4-1.  Pin Input/Output Circuit of List (1/2)
              Figure 4-1.  Pin Input/Output Circuit of List (2/2)
              CHAPTER 5  CPU ARCHITECTURE 5.1  Memory Spaces
Each product of the                 
PD78052, 78052Y)
              Figure 5-2.  Memory Map (
PD78053, 78053Y)              
Figure 5-3.  Memory Map (
PD78054, 78054Y)              
Figure 5-4.  Memory Map (
              Figure 5-5.  Memory Map (
PD78055, 78055Y)              
Figure 5-6.  Memory Map (
PD78056, 78056Y)              
Figure 5-7.  Memory Map (
PD78058, 78058Y)              
Figure 5-8.  Memory Map (
PD78P058,                 
PD78P058Y)
            Page
            Page
            Page
              Figure 5-10.  Data Memory Addressing (
PD78053, 78053Y)              
Figure 5-11.  Data Memory Addressing (
PD78054, 78054Y)              
Figure 5-12.  Data Memory Addressing (
              Figure 5-13.  Data Memory Addressing (
PD78055, 78055Y)              
Figure 5-14.  Data Memory Addressing (
PD78056, 78056Y)              
Figure 5-15.  Data Memory Addressing (
PD78058, 78058Y)              
Figure 5-16.  Data Memory Addressing (
PD78P058, 78P058Y)              
5.2  Processor Registers
            Page
              Figure 5-21.  Data to be Reset from Stack Memory
15 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1                
0 PC0
SP            
Page
              Figure 5-22.  General Register Configuration (a)  Absolute Name
(b)  Function Name            
Page
              Table 5-6.  Special-Function Register List (1/3)
              Table 5-6.  Special-Function Register List (2/3)
PD78058, 78P058, 78058Y and 78P058Y.                
Note This register is provided only in the 
            Page
              5.3  Instruction Address Addressing
            Page
            Page
              5.4  Operand Address Addressing
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              CHAPTER 6  PORT FUNCTIONS 6.1  Port Functions
The               
Table 6-1.  Port Functions (
PD78054 subseries) (1/2)              
Table 6-1.  Port Functions (
PD78054 subseries) (2/2)              
 Table 6-2.  Port Functions (
PD78054Y subseries) (1/2)              
Table 6-2.  Port Functions (
PD78054Y subseries) (2/2)              
6.2  Port Configuration
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              6.3  Port Function Control Registers
            Page
CHAPTER 6   PORT FUNCTIONS              
Figure 6-19.  Port Mode Register Format
            Page
              CHAPTER 6   PORT FUNCTIONS
            Page
              6.4  Port Function Operations
              6.5  Selection of Mask Option
            Page
            Page
              Figure 7-1.  Block Diagram of Clock Generator
              7.3  Clock Generator Control Register
CHAPTER 7   CLOCK GENERATOR              
Figure 7-3.  Processor Clock Control Register Format
              The fastest instruction of the 
Remarks 1. fX = 5.0 MHz, fXT = 32.768 kHz            
Page
              7.4  System Clock Oscillator
            Page
            Page
            Page
              7.5  Clock Generator Operations
            Page
              7.6  Changing System Clock and CPU Clock Settings
              Table 7-3.  Maximum Time Required for CPU Clock Switchover
            Page
            Page
              CHAPTER 8  16-BIT TIMER/EVENT COUNTER 8.1  Outline of Timers Incorporated in the 
PD78054, 78054Y Subseries            
Page
              8.2  16-Bit Timer/Event Counter Functions
            Page
              8.3  16-Bit Timer/Event Counter Configuration
Selector                
Note Refer to Figure 21-1. Basic Configuration of Interrupt Function.
Selector                
Note 2
              Figure 8-2.  16-Bit Timer/Event Counter Output Control Circuit Block Diagram
Remark The circuitry enclosed by the dotted line is the output control circuit.            
Page
              8.4  16-Bit Timer/Event Counter Control Registers
              Figure 8-3.  Timer Clock Selection Register 0 Format
            Page
            Page
            Page
              Figure 8-6.  16-Bit Timer Output Control Register Format
            Page
            Page
            Page
              8.5  16-Bit Timer/Event Counter Operations
              Figure 8-11.  Interval Timer Configuration Diagram
Figure 8-12.  Interval Timer Operation Timings                
Remark Interval time = (N + 1)  t : N = 0001H to FFFFH.
            Page
            Page
Switching Circuit TO0/P30                
PD78054, 78054Y
PWM signal                
)
              capture/compare register 00 (CR00) value
            Page
            Page
              Figure 8-18.  Configuration Diagram for Pulse Width Measurement by Free-Running Counter
            Page
            Page
            Page
            Page
            Page
            Page
              Figure 8-27.  External Event Counter Configuration Diagram
Figure 8-28.  External Event Counter Operation Timings (with Rising Edge Specified)                
Caution When reading the external event counter count value, TM0 should be read.
            Page
              Figure 8-30.  Square-Wave Output Operation Timing
Table 8-7.  16-Bit Timer/Event Count Square-Wave Output Ranges            
Page
              Figure 8-32.  Timing of One-Shot Pulse Output Operation Using Software Trigger
            Page
            Page
              8.6  16-Bit Timer/Event Counter Operating Precautions
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              9.2  8-Bit Timer/Event Counters 1 and 2 Configurations
CHAPTER 9   8-BIT TIMER/EVENT COUNTERS 1 AND 2              
Figure 9-1.  8-Bit Timer/Event Counters 1 and 2 Block Diagram
              Figure 9-2.  Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
              9.3  8-Bit Timer/Event Counters 1 and 2 Control Registers
CHAPTER 9   8-BIT TIMER/EVENT COUNTERS 1 AND 2              
Figure 9-4.  Timer Clock Select Register 1 Format
Caution When rewriting TCL1 to other data, stop the timer operation beforehand.            
Page
            Page
            Page
              9.4  8-Bit Timer/Event Counters 1 and 2 Operations
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              9.5  Cautions on 8-Bit Timer/Event Counters 1 and 2
            Page
            Page
              CHAPTER 10  WATCH TIMER 10.1  Watch Timer Functions
              10.2  Watch Timer Configuration
10.3  Watch Timer Control Registers              
Figure 10-1.  Watch Timer Block Diagram
              Figure 10-2.  Timer Clock Select Register 2 Format
4. : Don't care              
CHAPTER 10   WATCH TIMER
              10.4  Watch Timer Operations
              CHAPTER 11  WATCHDOG TIMER 11.1  Watchdog Timer Functions
            Page
CHAPTER 11   WATCHDOG TIMER              
11.2  Watchdog Timer Configuration
The watchdog timer consists of the following hardware. Table 11-3.  Watchdog Timer Configuration                
Control register
Selector            
Page
              Figure  11-2.  Timer Clock Select Register 2 Format
4. : Don't care            
Page
              11.4  Watchdog Timer Operations
            Page
            Page
              12.2  Clock Output Control Circuit Configuration
Control register            
Page
              Figure 12-3.  Timer Clock Select Register 0 Format
            Page
            Page
              CHAPTER 13  BUZZER OUTPUT CONTROL CIRCUIT 13.1  Buzzer Output Control Circuit Functions
13.2  Buzzer Output Control Circuit Configuration            
Page
CHAPTER 13   BUZZER OUTPUT CONTROL CIRCUIT              
Figure 13-2.  Timer Clock Select Register 2 Format
4. : don't care            
Page
              CHAPTER 14  A/D CONVERTER 14.1  A/D Converter Functions
14.2  A/D Converter Configuration                
CHAPTER 14   A/D CONVERTER
Selector                
Tap Selector
              Figure 14-1.  A/D Converter Block Diagram
            Page
            Page
            Page
              Figure 14-3.  A/D Converter Mode Register Format
Notes 1. Set so that the A/D conversion time is 19.1                 
s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 
              CHAPTER 14   A/D CONVERTER
            Page
              14.4  A/D Converter Operations
            Page
            Page
            Page
            Page
              14.5  A/D Converter Cautions
            Page
            Page
            Page
CHAPTER 15   D/A CONVERTER              
15.2  D/A Converter Configuration
The D/A converter consists of the following hardware. Table 15-1.  D/A Converter Configuration                
Register
            Page
              15.3  D/A Converter Control Registers
              15.4  Operations of D/A Converter
PD78054, 78054Y              
15.5  Cautions Related to D/A Converter
PD78054, 78054Y              
CHAPTER 16  SERIAL INTERFACE CHANNEL 0 (
              16.1  Serial Interface Channel 0 Functions
            Page
              16.2  Serial Interface Channel 0 Configuration
              Figure 16-2.  Serial Interface Channel 0 Block Diagram
Remark Output Control performs selection between CMOS output and N-ch open-drain output.            
Page
            Page
            Page
              Figure 16-3.  Timer Clock Select Register 3 Format
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.              
(Continued)
3. Can be used freely as port function.              
Figure 16-4.  Serial Operating Mode Register 0 Format (2/2)
              Figure 16-5.  Serial Bus Interface Control Register Format (1/2)
Remarks 1. Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are 0 when read after data setting.              
Figure 16-5.  Serial Bus Interface Control Register Format (2/2)
            Page
              16.4  Serial Interface Channel 0 Operations
            Page
              3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected. Remark :  dont care
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              (b) Serial bus interface control register (SBIC)
The shaded area is used in the SBI mode.                
(Continued)
            Page
            Page
              Figure 16-21.  RELT and CMDD Operations (Slave)
              Figure 16-22.  ACKT Operation
Caution Do not set ACKT before termination of transfer.              
Figure 16-23.  ACKE Operations (a)  When ACKE = 1 upon completion of transfer
(b)  When set after completion of transfer                
(d)  When ACKE = 1 period is short
(c)  When ACKE = 0 upon completion of transfer                
  SB0 (SB1)   ACKE If set and cleared during this period and ACKE = 0 at the falling edge of SCK0
              Figure 16-24.  ACKD Operations (a)  When ACK signal is output at 9th clock of SCK0
(b)  When ACK signal is output after 9th clock of SCK0                
Figure 16-25.  BSYE Operation
(c)  Clear timing when transfer start is instructed in BUSY              
Table 16-3.  Various Signals in SBI Mode (1/2)
              Table 16-3.  Various Signals in SBI Mode (2/2)
            Page
            Page
              Figure 16-27.  Address Transmission from Master Device to Slave Device (WUP = 1)
              Figure 16-28.  Command Transmission from Master Device to Slave Device
              Figure 16-29.  Data Transmission from Master Device to Slave Device
              Figure 16-30.  Data Transmission from Slave Device to Master Device
            Page
            Page
            Page
              3. Be sure to set WUP to 0 when the 2-wire serial I/O mode.
            Page
            Page
            Page
            Page
            Page
            Page
              CHAPTER 17  SERIAL INTERFACE CHANNEL 0 (
              17.1  Serial Interface Channel 0 Functions
            Page
              17.2  Serial Interface Channel 0 Configuration
              Figure 17-2.  Serial Interface Channel 0 Block Diagram
Remark Output Control selects between CMOS output and N-ch open drain output.            
Page
            Page
            Page
              Figure 17-3.  Timer Clock Select Register 3 Format
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.            
Page
              Figure 17-4.  Serial Operating Mode Register 0 Format
              Figure 17-5.  Serial Bus Interface Control Register Format (1/2)
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, ACKT) are 0 when read after the data is set.            
Page
              Notes 1. Bit 6 (CLD) is a read-only bit. 2. When not using the I2C mode, set CLC to 0.
            Page
              17.4  Serial Interface Channel 0 Operations
              3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
            Page
            Page
            Page
            Page
              3. Be sure to set WUP to 0 when the 2-wire serial I/O mode.
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
<6> <5> <4> <3> <2> <1> <0><7>              
(continued)
Symbol SBIC BSYE ACKD ACKE FF61H              00H           R/W                
Address     After Reset     R/W ACKT CMDD RELD CMDT RELT
            Page
              <6> <5> <4> <3> <2> 1 07
Symbol SINT 0 CLD SIC FF63H              00H           R/W                
Address     After Reset     R/W SVAM CLC WREL WAT1 WAT0
            Page
            Page
            Page
              (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Address
              (Both Master and Slave Selected 9-Clock Wait) (2 of 3) (b) Data
              (Both Master and Slave Selected 9-Clock Wait) (3 of 3) (c) Stop Condition
              (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Address
              (Both Master and Slave Selected 9-Clock Wait) (2 of 3) (b) Data
              (Both Master and Slave Selected 9-Clock Wait) (3 of 3) (c) Stop Condition
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              CHAPTER 18  SERIAL INTERFACE CHANNEL 1 18.1  Serial Interface Channel 1 Functions
              18.2  Serial Interface Channel 1 Configuration
              Figure 18-1.  Serial Interface Channel 1 Block Diagram
/2                
/2f
f                
Timer Clock Select Register 3
            Page
            Page
              Figure 18-2.  Timer Clock Select Register 3 Format
Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand.              
PM :  Port mode register
            Page
              2636
2628 0.5 fXX fXX fSCK              
Figure 18-5.  Automatic Data Transmit/Receive Interval Specify Register Format (2/4)
2. Zero must be set in bits 5 and 6.                
2628
2636              
Figure 18-5.  Automatic Data Transmit/Receive Interval Specify Register Format (3/4)
28                
36
              Figure 18-5.  Automatic Data Transmit/Receive Interval Specify Register Format (4/4)
28                
36
              18.4  Serial Interface Channel 1 Operations
              PM :  Port mode register
            Page
            Page
            Page
              PM:  Port mode register
            Page
              Minimum = (n+1)  + + ,  Maximum = (n+1) ++
2. Zero must be set in bits 5 and 6.                
28 0.5 26
            Page
            Page
            Page
            Page
            Page
              Figure 18-9.  Basic Transmission/Reception Mode Flowchart
            Page
              (c)  Completion of transmission/reception
            Page
              Figure 18-12.  Basic Transmission Mode Flowchart
            Page
              (c)  Completion of transmission
            Page
              Figure 18-15.  Repeat Transmission Mode Flowchart
            Page
              (c)  7th byte transmission point
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              CHAPTER 19  SERIAL INTERFACE CHANNEL 2 19.1  Serial Interface Channel 2 Functions
              19.2  Serial Interface Channel 2 Configuration
              Figure 19-1.  Serial Interface Channel 2 Block Diagram
/2                
-f
Note See Figure 19-2 for the baud rate generator configuration.              
Figure 19-2.  Baud Rate Generator Block Diagram
            Page
              19.3  Serial Interface Channel 2 Control Registers
              Figure 19-4.  Asynchronous Serial Interface Mode Register Format
              Table 19-2.  Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode
PM70 P70 PM71 P71 PM72 P72                
Note1 
(2) 3-wire Serial I/O Mode                
(3) Asynchronous Serial Interface Mode
            Page
              Figure 19-6.  Baud Rate Generator Control Register Format (1/2)
            Page
            Page
            Page
              19.4  Serial Interface Channel 2 Operation
            Page
            Page
            Page
            Page
              (d) Baud rate generator control register (BRGC)
Remark fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0  k 14)                
(continued)
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
              (c) Baud rate generator control register (BRGC)
Remark fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0  k 14)            
Page
            Page
            Page
               
            Page
            Page
              [Example]
            Page
              20.2  Real-Time Output Port Configuration
            Page
              20.3  Real-Time Output Port Control Registers
            Page
            Page
            Page
              21.2  Interrupt Sources and Configuration
              Table 21-1.  Interrupt Source List (2/2)
              Figure 21-1.  Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
(B) Internal maskable interrupt                
(C) External maskable interrupt (INTP0)
            Page
              21.3  Interrupt Function Control Registers
            Page
            Page
            Page
            Page
              Figure 21-6.  External Interrupt Mode Register 1 Format
            Page
            Page
            Page
              21.4  Interrupt Servicing Operations
              Figure 21-10.  Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment
TMIF4 : Watchdog timer interrupt request flag                
Instruction Instruction  CPU Instruction TMIF4
            Page
            Page
              Figure 21-13.  Interrupt Request Acknowledge Processing Algorithm
Start   IF=1?   MK=0?   PR=0?                
IE=1?
IE=1? ISP=1?              
Figure 21-14.  Interrupt Request Acknowledge Timing (Minimum Time)
f                
1
1 Remark 1 clock :        (fCPU: CPU clock)            
Page
            Page
            Page
            Page
              21.5  Test Functions
              Caution Be sure to set bits 3 through 6 to 1.
            Page
            Page
              CHAPTER 22   EXTERNAL DEVICE EXPANSION FUNCTION 22.1  External Device Expansion Functions
              PD78P054, 78P058, (b) Memory map of 
PD78052, 78052Y 78P058Y when the                 
PD78P054, 78P058, 78P058Y when the 
PD78053, 78053Y and internal PROM are 16 Kbytes and internal PROM are 24 Kbytes              
Figure 22-1.  Memory Map when Using External Device Expansion Function (2/4) (c) Memory map of 
PD78P054, 78P058, (d) Memory map of                 
PD78054, 78054Y when the 
PD78P058, 78P058Y 78P058Y when the                 
PD78055, 78055Y and and internal PROM are 32 Kbytes internal PROM are 40 Kbytes
              Figure 22-1.  Memory Map when Using External Device Expansion Function (3/4) (e) Memory map of 
PD78P058, 78P058Y when the                 
PD78056, 78056Y and internal PROM are 48 Kbytes
CHAPTER 22   EXTERNAL DEVICE EXPANSION FUNCTION              
Figure 22-1.  Memory Map when Using External Device Expansion Function (4/4) (f)
PD78058, 78058Y, 78P058, 78P058Y Memory (g)                
22.2   External Device Expansion Function Control Register
CHAPTER 22   EXTERNAL DEVICE EXPANSION FUNCTION              
PD78058, 78058Y CFH
PD78052, 78052Y 44H                
PD78053, 78053Y C6H
PD78054, 78054Y C8H                
PD78055, 78055Y CAH
              22.3  External Device Expansion Function Timing
              Figure 22-4.  Instruction Fetch from External Memory
Lower Address Operation Code Higher Address              
Figure 22-5.  External Memory Read Timing
              Figure 22-6. External Memory Write Timing
              Figure 22-7.  External Memory Read Modify Write Timing
              22.4  Example of Connection with Memory
This section provides                 
PD78054 and Memory
            Page
              CHAPTER 23   STANDBY FUNCTION 23.1  Standby Function and Configuration
              m
STOP Mode Clear X1 Pin Voltage Waveform V                
a
CHAPTER 23   STANDBY FUNCTION              
23.2  Standby Function Operations
Notes 1. Including when external clock is not supplied 2. Including when external clock is supplied            
Page
              Remark    x:  Don't care
            Page
            Page
            Page
              CHAPTER 24  RESET FUNCTION 24.1  Reset Function
              Figure 24-2.  Timing of Reset Input by RESET Input
Figure 24-3.  Timing of Reset due to Watchdog Timer Overflow                
Figure 24-4.  Timing of Reset Input in STOP Mode by RESET Input
            Page
            Page
              CHAPTER 25   ROM CORRECTION 25.1  ROM Correction Functions
25.2  ROM Correction Configuration            
Page
              25.3  ROM Correction Control Registers
Note Bits 0 and 2 are read-only bits.              
25.4  ROM Correction Application
Figure 25-5.  Connecting Example with EEPROM (using 2-wire serial I/O mode)                
PD78058, 78058Y EEPROM
EEPROM Source program            
Page
              Figure 25-7.  ROM Correction Operation
              25.5  ROM Correction Example
              25.6  Program Execution Flow
            Page
              25.7  Cautions on ROM Correction
              CHAPTER 26  
PD78P054, 78P058                
PD78P054 and the 
PD78P054, 78P058 replace the internal mask ROM of the                 
PD78P058  applies to both the 
            Page
              26.1  Memory Size Switching Register (
Figure 26-1.  Memory Size Switching Register Format (                
Relevant Mask ROM Version IMS Setting
PD78052 44H                
PD78053 C6H
              26.2  Memory Size Switching Register (
PD78P058)                
PD78058, 78058Y CFH
The                 
PD78P058)
              26.3  Internal Expansion RAM Size Switching Register
              26.4  PROM Programming
            Page
Remark: G  = Start address N  =  Last address of program              
26.4.2  PROM write procedure Figure 26-4.  Page Program Mode Flowchart
              Figure 26-5.  Page Program Mode Timing
              Remark: G  =  Start address N  =  Last address of program
Figure 26-6.  Byte Program Mode Flowchart              
Figure 26-7.  Byte Program Mode Timing
            Page
              26.5  Erasure Procedure (
PD78P054KK-T and 78P058KK-T Only)                
26.6  Opaque Film Masking the Window (
PD78P054KK-T and 78P058KK-T Only)                
26.7  Screening of One-Time PROM Versions
            Page
            Page
              27.1  Legends Used in Operation List
            Page
              27.2  Operation List
              3. Only when rp = BC, DE or HL 4. Except "r = A"
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
            Page
              Figure B-1.  Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS
              Figure B-1.  Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A
              B.1  Language Processing Software
            Page
              B.2  PROM Writing Tools
              B.3  Debugging Tools
            Page
            Page
            Page
              B.4  OS for IBM PC
B.5  Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A            
Page
              Based on EV-9200GC-80 (2) Pad drawing (in mm)
              TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm)
              APPENDIX  C   EMBEDDED SOFTWARE
Real-time OS (1/2)              
Real-time OS (2/2)
              APPENDIX D   REGISTER INDEX D.1  Register Index
            Page
            Page
            Page
              APPENDIX E   REVISION HISTORY
Major revisions by edition and revised chapters are shown below.            
Page
            Page
            Page
              Facsimile
Message                
Thank you for your kind support.
From: