4.5.5. CPU ASIC ( IC1 ) overview

The CPU_ASIC ( IC 1) is a high-performance integrated printer processor that combines a CPU core, a bit block transfer (BitBLT)
controller, a video data generator(VDG), and numerous printer controller features on a single chip.
The CPU_ASIC has the function macro modules as follows.
- CPU - USB I/F
- SDRAM I/F - PCI I/F (for Network I/F)
- ROM I/F - Timer
- VDG - IO I/F
- BitBLT - IEEE1284 I/F
The CPU_ASIC controls the following functions.
· Process the print data from host PC
· Initialization and control of Memories (ROM/Flash/SDRAM)
· Control the Interface (USB/ IEEE1284/ PCI/ Engine) port
· Control of LED and detection of key on the front panel
The CPU_ASIC ( IC1) has the following three types of external bus interface for connection with peripheral devices.
· ROM Bus
· SDRAM Bus
· PCI Bus
The ROM Bus, which operates asynchronously with the CPU clock, is to be used for connection with the Mask ROM or the Flash
ROM devices (IC3, Option ROM CN) and controls the devices directly. The SDRAM Bus, which is synchronized with the CPU clock
(100MHz),is the bus to be used for connection with the SDRAM Devices (IC5, Option RAM CN) and controls the devices directly.
The PCI Bus, which is synchronized with the 1/4 CPU clock (25MHz), is the bus to be used for connection with the Mac & Phy
(MediaAccess Controller & Physical Layer) device (IC6).
The Block Diagram of CPU_ASIC(IC1) is as follows.
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KX-P7105 / KX-P7110