Panasonic KX-P7105, KX-P7110 4.5.5.2. SDRAM I/F

4.5.5.2. SDRAM I/F
The CPU ASIC ( IC1 ) integrates a high-performance memory controller. The SDRAM I/F, which is the basic macro in CPU ASIC
( IC1 ) for controlling external SDRAM devices.
The control signals of SDRAM devices are as follows.
SDMA [11:0]: These signals constitute the external SDRAM address bus.
SDDATA [15:0]: These signals constitute a bidirectional data bus for external SDRAM.
SDBA [1:0]: These signals constitute the external SDRAM Bank address.
SDDQM [1:0]: These are the data mask output signals for external SDRAM.
SDCKE: This is the clock enable output signal for external SDRAM.
SDWE: This is the data write enable output signal for external SDRAM.
SDCAS: This is the column address strobe output signal for external SDRAM.
SDRAS: This is the row address strobe output signal for external SDRAM.
nSDCS [0]: These are the chip select output signals for the standard SDRAM device.
nSDCS [1] These are the chip select output signals for optional SDRAM devices.
SDCLK: This is the synchronization clock output signal for external SDRAM.
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KX-P7105 / KX-P7110