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| SECTION 4 | |
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| EXPLANATION OF IC TERMINALS | ||
IC602, 604 CDX2707Q (DSP) |
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Pin No. |
| Pin name | I/O |
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| Description | ||
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1 |
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| EA9 | 0 |
| External install RAM address. Not used (OPEN) | ||
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2 |
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| ECO | 0 |
| External install RAM address. Not used (OPEN) | ||
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3 |
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| VDD | - |
| Power supply. (+5V) | ||
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4 |
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| Vss | - |
| Power supply. (GND) | ||
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5,6 |
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| ECl- 2 | 0 |
| External install RAM address. Not used (OPEN) | ||
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7 - 9 |
| EA13 - 15 | 0 |
| External install RAM address. Not used (OPEN) | |||
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10 |
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| TST |
| I |
| Test data input. | "L": Normal |
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11 |
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| TDR |
| I |
| Test data input. | "L": Normal |
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12 |
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| BFOT | 0 |
| Master cIock buffer output. Not used (OPEN) | ||
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13 |
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| CLKO | 0 |
| Master cIock output. Not used (OPEN) | ||
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14 |
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| CLKI |
| I |
| Master cIock input. |
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15 |
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| Vss | - |
| Power supply. (GND) | ||
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16 |
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| TSO |
| I |
| Test data input. | "L": Normal |
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17 |
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| TS1 |
| I |
| Test data input. | "L": Normal |
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18 |
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| TSA |
| I |
| Test data input. | "L": Normal |
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19 |
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| LRKO |
| I |
| LRCK input. |
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20 |
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| LRK1 |
| I |
| LRCK input. |
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21 |
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| BCKO |
| I |
| BCK input. |
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22 |
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| BCK1 |
| I |
| BCK input. |
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23 |
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| BCT | 0 |
| Frequency divider BCK output. | ||
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24 |
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| LCT | I/O |
| Counter input/frequency divider LRCK output for SYNC DET. | ||
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25 |
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| SIA |
| I |
| Serial data input. |
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26 |
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| SIB |
| I |
| Serial data input. |
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27 |
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| SIC |
| I |
| Serial data input. |
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28 |
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| VDD | - |
| Power supply. (+5V) | ||
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29 |
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| Vss | - |
| Power supply. (GND) | ||
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30 |
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| SOA | 0 |
| Serial data output. |
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31 |
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| SOB | 0 |
| Serial data output. |
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32 |
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| SOC | 0 |
| Serial data output. |
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33 |
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| EClO | I/O |
| Terminal input/test data output for conditional jump. | ||
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34 |
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| ECll | I/O |
| Terminal input/test data output for conditional jump. | ||
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35 |
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| ECl2 | I/O |
| Terminal input/test data output for conditional jump. Not used (GND connection) | ||
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36 |
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| ECJ3 | I/O |
| Terminal input/test data output for conditional jump. Not used (GND connection) | ||
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37 |
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| REDY | 0 |
| HCIF Readay signal output. (Open drain) | ||
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38 |
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| TRDT | 0 |
| HCIF data output. |
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39 |
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| XLAT |
| I |
| HCIF data • mode identification signal input. | |
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40 |
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| Vss | - |
| Power supply. (GND) | ||
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41 |
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| SCK | 0 |
| HCIF shift cIock output. | ||
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42 |
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| RVDT |
| I |
| HCIF data input. |
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43 |
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| SCLO | 0 |
| Test data output. Not used (OPEN) | ||
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44 |
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| SCL1 | 0 |
| Test data output. Not used (OPEN) | ||
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- 20-
