5. SCHEMATIC DIAGRAM — MAIN SECTION (3/3) —
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Note:
•All capacitors are in µF unless otherwise noted. pF: µµF 50 WV or less are not indicated except for electrolytics and tantalums.
•All resistors are in Ω and 1/4 W or less unless otherwise specified.
•% : indicates tolerance.
•C : panel designation.
•A : B+ Line.
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• Power voltage is dc 4.5 V and fed with regulated dc power | • Signal path. | |||
supply from external power voltage jack. |
| F : PB (analog) | ||
• Voltage is dc with respect to ground under | L : REC (analog) | |||
condition. |
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| J : PB (digital) | |
no mark : PB |
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| c : REC (digital) | |
( | ) : REC |
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•Voltages are taken with a VOM (Input impedance 10 MΩ). Voltage variations may be noted due to normal produc- tion tolerances.
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