PRINCIPLES OF OPERATION
CN4
DATA 1
DATA 2
DARA 3
DATA 4
DATA 5
DARA 6
DATA 7
DATA 8
STROBE
IC5
BUSY
ACK
ERROR
SELECT
PAPER OUT
LS05
IC4
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CSTB
BUSY
ACK
ERROR
SELECT
POUT
Gate array
IC1
CPU
Fig. 2-3 Parallel interface
When the printer is ready (BUSY is LOW), the host computer transmits eight bits of parallel data (DATA1,...,DATA8) to CN4. The data passes through the gate array and moves into the CPU.
Printer signals from the CPU (ACK, ERROR, SELECT, PAPER OUT, etc.) pass through the gate array and are output over the appropriate connector pins.
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