Chapter 1: Introduction
1-2 Chipset Overview
Built upon the functionality and the capability of the E7520 Lindenhurst chipset, The X6DH8-G2/X6DHE-G2 motherboard provides the performance and feature set required for dual processor-based servers, with configura- tion options optimized for communications, presentation, storage, computa- tion or database applications. The Intel E7520 Lindenhurst chipset consists of the following components: the Lindenhurst Memory Controller Hub (MCH), the 82801ER I/O Controller Hub 5-R (ICH5-R), and the Intel PCI-X Hub.
The E7520 Lindenhurst MCH supports single or dual Nocona processors with Front Side Bus speeds of up to 800 MHz(*Note). Its memory controller provides direct connection to two channels of registered DDR2- 400 with a marched system bus address and data bandwidths of up to 6.4GB/s. The Lindenhurst also supports the new PCI Express high speed serial I/O inter- face for superior I/O bandwidth. The MCH provides three configurable x8 PCI Express interfaces which may alternatively be configured as two inde- pendent x4 PCI Express interfaces. These interfaces support connection of the MCH to a variety of other bridges that are compliant with the PCI Ex- press Interface Specification, Rev. 1.0a. The MCH interfaces with the 82801ER I/O Controller Hub 5-R (ICH5R) via a dedicated Hub Interface sup- porting a peak bandwidth of 266 MB/s using a x4 base clock of 66 MHz. The PXH provide connection between a PCI Express interface and two indepen- dent PCI bus interfaces that can be configured for standard PCI 2.3 proto- col, as well as the enhanced high-frequency PCI-X protocol. The PXH can be configured to support for 32- or 64-bit PCI devices running at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.
The ICH5R I/O Controller Hub provides legacy support similar to that of previous ICH-family devices, but with extensions in RAID 0,1 support, Serial ATA Technology, and an integrated ASF Controller. In addition, the ICH5R also provides various integrated functions, including a two-channel Ultra ATA/100 bus master IDE controller, USB 2.0 host controllers, an integrated 10/100 LAN controller, an LPC firmware hub (FWH) and Super IO interface, a System Management Interface, a power management interface, integrated IOxAPIC and 8259 interrupt controllers.
