Theory of Operation 4-9
♦Supports the most flexible six 32-bit populated banks of DRAM (to spare
12 MB for Windows 95)
♦Supports SIMM and DIMM
♦UMA (unified memory architecture)
♦Dedicated UMA arbiter pins
♦Supports several protocols from major graphics vendors
♦SFB size : 512 KB/1 MB/2 MB/3 MB/4 MB
♦CPU could access frame buffer memory through system memory controller
♦Alias address for frame buffer memory
♦Fully synchronous 25/30/33 MHz 5V PCI interface
♦PCI bus arbiter: five PCI masters and M1523 supported
♦DWORDs for CPU-to-PCI Memory write posted buffers
♦Convert back-to-back CPU to PCI memory write to PCI burst cycle
♦DWORDS for PCI-to-DRAM write-posted/Read-prefetching buffers
♦PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-back)
♦L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle
♦Supports PCI mechanism #1 only
♦PCI spec. 2.1 support (N(16/8)+8 rule, passive release, fair arbitration)
♦Enhanced performance for memory-read-line, memory-read-multiple, and
memory-write-multiple
♦Invalidates PCI commands
♦DRAM refresh during 5V system suspend
♦I/O leakage stopper for power saving during system suspend
4.2.3.2 ALI M1523 (PCI-ISA Bridge)
The M1523 provides a bridge between the PCI bus and the ISA bus and ensures full
compatibility between the PCI and ISA functions. The M1523 has an Integrated System
Peripherals (ISP) chip that provides advanced DMA controller features. This chip
contains the keyboard controller, real time clock and IDE master controller. This chip
also supports the Advanced Programmable Interrupt controller (APIC) interface.