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Texas Instruments PCI445X ±1. Registers and Bits Loadable Through Serial EEPROM, Register Offset

Models: PCI445X

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			System Implementation
	Table 1±1. Registers and Bits Loadable Through Serial EEPROM

Register Offset		Register	Bits Loaded From
			EEPROM

	The following are configuration registers for the OHCI function (function 2)

PCI register (2Ch)		PCI subsystem ID	15±0

PCI register (2Dh)		PCI vendor ID	15±0

PCI register (3Eh)		PCI maximum latency, minimum grant	11±8, 3±0

PCI register (F0h)		PCI miscellaneous configuration	15, 13, 10, 3±0

PCI register (F4h)		Link enhancements control	7, 2, 1

OHCI register (24h)		1394 global unique ID Hi	31±0

OHCI register (28h)		1394 global unique ID Lo	31±0

	The following are configuration registers for PC Card functions (functions 0 and 1)

PCI register (40h)		Subsystem vendor ID	15±0

PCI register (42h)		Subsystem ID	15±0

PCI register (80h)		System control	31±24, 22±14, 6±3, 1, 0

PCI register (86h)		General control	3±0

PCI register (89h)		General-purpose event enable	7, 6, 3±0

PCI register (8Bh)		General-purpose output	3±0

PCI register (8Ch)		Multifunction routing	30±28, 26±24, 22±20,
			18±16, 14±12, 10±8,
			6±4, 2±0

PCI register (91h)		Card control	7, 6, 2±0

PCI register (92h)		Device control	7, 6, 2±0

PCI register (93h)		Diagnostic	7, 5, 0

PCI register (A2h)		Power management capabilities	15

PCI register		ExCA ID and revision	7±0

PCI445X Device

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Texas Instruments PCI445X ±1. Registers and Bits Loadable Through Serial EEPROM, Register Offset, Bits Loaded From, Eeprom

Contents

Implementation Guide PCI Bus SolutionsAugust SCPU007IMPORTANT NOTICE Read This First How to Use This ManualAbout This Manual Notational ConventionsLALK 16±bit constant , shift asect ªsection nameº, addressbyte value1 , ... , valuen C csr ±a /user/ti/simuboard/utilitiesOHCI.Lynx Configuration Information Application Report, SLLA077 PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046TSB41LV03A Data Sheet, SLLS364 Related Documentation From Texas InstrumentsPage Contents A Global Reset Only Bits, PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 1±1 Typical System Architecture 1±2 Serialized Interrupt Signal Figures1±3 EEPROM 2-Wire Interface 1±4 TPS22X6 Power Switch Interface 1±5 Example of a ZV Interface 1±6 Distributed DMA Signal ConnectionTables Chapter PCI445X DevicePage TopicFigure 1±1. Typical System Architecture 1.1.3 PME and RI Signaling 1.1 System Features Selection1.1.1 Package Types 1.1.2 GRST and PRST1.1.9 Optional PCI Signals 1.1.7 Socket Power Switches1.1.6 PCI and ISA Style Interrupt 1.1.8 Distributed DMA DDMA1.1.10 Socket Activity LEDs Figure 1±2. Serialized Interrupt Signal1.1.11 MFUNC7±MFUNC0 Terminal Assignments 1.1.12 Miscellaneous Functions Description1.1.12.6 Power Savings Mode 1.1.12.4 CardBus Reserved Terminal Signaling1.1.12.3 Asynchronous CSC Interrupt Generation 1.1.12.5 Memory Burst R/W Operation Control1.1.12.9 SMI 1.1.12.10 Socket Power Lock1.1.12.11VCC Protection 1.1.12.12 ZV Port Control and Auto Detect Function1.2.1 Clamping Rails 1.2 System Implementation1.2.2 PCI Bus Interface PCLK, AD31±AD0, C/BE3±C/BE0, PAR, DEVSEL, FRAME, STOPINTA, INTB, and INTC PRST PCI reset and GRST Global resetCLKRUN Note Pullup Resistor RequirementsFigure 1±3. EEPROM 2-Wire Interface 1.2.4 2-Wire I2C Interface for EEPROMSocket power supply 1.2.3 PC Card InterfaceRegister Offset Table 1±1. Registers and Bits Loadable Through Serial EEPROMRegister Bits Loaded FromFollowing is an example EEPROM data file used with the PCI445X device 1.3 Sample PCI445X EEPROM Data File1D 0xFF 1E 0xFF 1F 0xFF Figure 1±4. TPS22X6 Power Switch Interface 1.3.1 P2C Interface for TPS22X6 Power Switch1.3.2 Zoomed Video ZV Interface Figure 1±5. Example of a ZV Interface1.3.4 Miscellaneous Signals 1.3.3 Interrupt Signaling InterfaceSerialized Interrupt Interface Parallel PCI Interrupt1.3.5 Requirement of Pullup/Pulldown Resistors Figure 1±6. Distributed DMA Signal ConnectionTable 1±2. PC Card Interface Pullup Resistor List² ³ System ImplementationTable 1±4. Miscellaneous Terminals Pullup Resistor List Table 1±3. PCI Bus Interface Pullup Resistor ListSignal Table 1±5. Required Pullup/Pulldown ResistorsPulldown Default System ImplementationCommand register PCI offset 04h 16-bit 1.4 BIOS ConsiderationsLatency timer PCI offset 0Dh 8-bit CardBus latency timer register PCI offset 1Bh 8-bit1.4.2 System Sleeping State Consideration Power management control/status register PCI offset A4h 16-bit1.4.1.2 PCI TI Proprietary Registers Initialization 1 SUSPEND1.4.3 Docking System Consideration 2 Register save/restore1.5 Important Information 1.5.4 Socket Power Control1.5.1 GRST Clamping Rail 1.5.2 PME/RIOUT Bit DefinitionTopic Appendix AGlobal Reset Only Bits, PME Context Bits PageTable A±1.Global Reset Only Cleared Bits A.1 Global Reset Only Bits/PME Context BitsTable A±2.PME Context Bits Page Appendix B PME and RI BehaviorTopic PageTable B±1.CardBus CTSCHG and Wake-Up Signals Truth Table Table B±2.16-Bit Card RI/STSCHG and Wake-Up Signals Truth TableB.1 PME and RI Behavior Appendix C PCI445X Buffer TypesTopic PagePCI445X Buffer Types Table C±1. PCI445X Terminal Function Assignment and Buffer TypesPCI445X Buffer Types Signal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalPCI445X Buffer Types Table C±2. Buffer Type AbbreviationsBuffer Type Description