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Texas Instruments PCI445X Important Information, GRST Clamping Rail, Serialized IRQ Data Stream

Models: PCI445X

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1.5 Important Information

Important Information

1.5 Important Information

This section clarifies important system implementation.

1.5.1G_RST Clamping Rail

G_RST is clamped to VCCP, so removing VCCP causes assertion of G_RST.

Figure 1±7. G_RST and VCCP Relationship

VCCP	VCCP = 0
	VCCP
	removed
G_RST	G_RST

All other signals with clamping rails behave the same way.

1.5.2PME/RI_OUT Bit Definition

If PME is selected, only PME is signaled on the PME/RI_OUT terminal. If RI_OUT is selected, only RI_OUT is signaled. The PCI445X device can signal PME and RI_OUT as completely separated signals. In this case RI_OUT should be assigned on the MFUNC terminal.

1.5.3Serialized IRQ Data Stream

PCI clock is needed for operation of the PCI445X serialized IRQ state-machine. During SUSPEND assertion, the PCI445X device stops the IRQSER stream. Before asserting SUSPEND, IRQSER must be stopped.

1.5.4Socket Power Control

An internal or external CLOCK source is needed for the socket power control through the P2C interface. The internal ring oscillator is on while the core VCC is applied to the PCI445X device. External CLOCK source is dependent on the system.

1.5.5External CLOCK Frequency for P2C Interface

If an external P2C CLOCK is used, then it will affect:

Advanced CD line noise filtering

VS test speed

TPS22X6 power control interface speed

Use of the internal ring oscillator is recommended. Recommended external CLOCK source is the 32.768-kHz real-time clock (RTC).

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Texas Instruments PCI445X Important Information, GRST Clamping Rail, 1.5.2 PME/RIOUT Bit Definition, Socket Power Control

Contents

PCI Bus Solutions Implementation GuideAugust SCPU007IMPORTANT NOTICE How to Use This Manual Read This FirstAbout This Manual Notational Conventionsasect ªsection nameº, address LALK 16±bit constant , shiftbyte value1 , ... , valuen C csr ±a /user/ti/simuboard/utilitiesPCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046 OHCI.Lynx Configuration Information Application Report, SLLA077TSB41LV03A Data Sheet, SLLS364 Related Documentation From Texas InstrumentsPage Contents A Global Reset Only Bits, PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Figures 1±1 Typical System Architecture 1±2 Serialized Interrupt Signal1±3 EEPROM 2-Wire Interface 1±4 TPS22X6 Power Switch Interface 1±5 Example of a ZV Interface 1±6 Distributed DMA Signal ConnectionTables PCI445X Device ChapterPage TopicFigure 1±1. Typical System Architecture 1.1 System Features Selection 1.1.3 PME and RI Signaling1.1.1 Package Types 1.1.2 GRST and PRST1.1.7 Socket Power Switches 1.1.9 Optional PCI Signals1.1.6 PCI and ISA Style Interrupt 1.1.8 Distributed DMA DDMAFigure 1±2. Serialized Interrupt Signal 1.1.10 Socket Activity LEDs1.1.11 MFUNC7±MFUNC0 Terminal Assignments 1.1.12 Miscellaneous Functions Description1.1.12.4 CardBus Reserved Terminal Signaling 1.1.12.6 Power Savings Mode1.1.12.3 Asynchronous CSC Interrupt Generation 1.1.12.5 Memory Burst R/W Operation Control1.1.12.10 Socket Power Lock 1.1.12.9 SMI1.1.12.11VCC Protection 1.1.12.12 ZV Port Control and Auto Detect Function1.2 System Implementation 1.2.1 Clamping Rails1.2.2 PCI Bus Interface PCLK, AD31±AD0, C/BE3±C/BE0, PAR, DEVSEL, FRAME, STOPPRST PCI reset and GRST Global reset INTA, INTB, and INTCCLKRUN Note Pullup Resistor Requirements1.2.4 2-Wire I2C Interface for EEPROM Figure 1±3. EEPROM 2-Wire InterfaceSocket power supply 1.2.3 PC Card InterfaceTable 1±1. Registers and Bits Loadable Through Serial EEPROM Register OffsetRegister Bits Loaded From1.3 Sample PCI445X EEPROM Data File Following is an example EEPROM data file used with the PCI445X device1D 0xFF 1E 0xFF 1F 0xFF 1.3.1 P2C Interface for TPS22X6 Power Switch Figure 1±4. TPS22X6 Power Switch Interface1.3.2 Zoomed Video ZV Interface Figure 1±5. Example of a ZV Interface1.3.3 Interrupt Signaling Interface 1.3.4 Miscellaneous SignalsSerialized Interrupt Interface Parallel PCI InterruptFigure 1±6. Distributed DMA Signal Connection 1.3.5 Requirement of Pullup/Pulldown ResistorsTable 1±2. PC Card Interface Pullup Resistor List² ³ System ImplementationTable 1±3. PCI Bus Interface Pullup Resistor List Table 1±4. Miscellaneous Terminals Pullup Resistor ListTable 1±5. Required Pullup/Pulldown Resistors SignalPulldown Default System Implementation1.4 BIOS Considerations Command register PCI offset 04h 16-bitLatency timer PCI offset 0Dh 8-bit CardBus latency timer register PCI offset 1Bh 8-bitPower management control/status register PCI offset A4h 16-bit 1.4.2 System Sleeping State Consideration1.4.1.2 PCI TI Proprietary Registers Initialization 1 SUSPEND2 Register save/restore 1.4.3 Docking System Consideration1.5.4 Socket Power Control 1.5 Important Information1.5.1 GRST Clamping Rail 1.5.2 PME/RIOUT Bit DefinitionAppendix A TopicGlobal Reset Only Bits, PME Context Bits PageA.1 Global Reset Only Bits/PME Context Bits Table A±1.Global Reset Only Cleared BitsTable A±2.PME Context Bits Page PME and RI Behavior Appendix BTopic PageB.1 PME and RI Behavior Table B±1.CardBus CTSCHG and Wake-Up Signals Truth TableTable B±2.16-Bit Card RI/STSCHG and Wake-Up Signals Truth Table PCI445X Buffer Types Appendix CTopic PagePCI445X Buffer Types PCI445X Buffer TypesTable C±1. PCI445X Terminal Function Assignment and Buffer Types Signal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalTable C±2. Buffer Type Abbreviations PCI445X Buffer TypesBuffer Type Description