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Texas Instruments PCI445X 1.3.1 P2C Interface for TPS22X6 Power Switch, Zoomed Video ZV Interface

Models: PCI445X

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1.3.1P2C Interface for TPS22X6 Power Switch

System Implementation

1.3.1P2C Interface for TPS22X6 Power Switch

The interface between the PCI445X device and TPS22X6 power switch is serialized to reduce the number of signal lines. The P2C interface requires only three lines to control the switch. As a PCI445X default, the CLOCK signal is selected from an external source. It is usually provided from RTC, 32.768 kHz. The PCI445X device can also generate this clock from an internal ring oscillator. The typical frequency of the internal ring oscillator is 16 kHz. If using the internal clock source, then a pulldown resistor is required on the CLOCK terminal. If arranging for D3 wake implementation, then connect the power switch RESET terminal to GRST.

Figure 1±4. TPS22X6 Power Switch Interface

			VPPA
VCCA	CLOCK		VCCA
VCCA	VCCB	TPS22X6	VPPB
	DATA	TPS22X6	VPPB
PCI445X
	LATCH		VCCB
		Pulldown on
		CLOCK

1.3.2Zoomed Video (ZV) Interface

SLOT

A

SLOT

B

The PCI445X device has an internally buffered and selectable ZV interface. It supports three ZV sources, two from PC Cards and one from an external source. An auto ZV detect function provides software independent ZV switching. The auto ZV detect function senses the pixel clocks, arbitrates three inputs, and selects one of them according to priority bits.

Figure 1±5. Example of a ZV Interface

3rd ZV Source

Buffer

SLOT

A

SLOT

B

23

23

ZVPCLK ZVSTAT

PCI445X

19	Graphic
	Controller
4	Audio	Stereo
	Codec

Sound

Controller

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Texas Instruments PCI445X manual 1.3.1 P2C Interface for TPS22X6 Power Switch, ±4. TPS22X6 Power Switch Interface

Contents

PCI Bus Solutions Implementation GuideAugust SCPU007IMPORTANT NOTICE How to Use This Manual Read This FirstAbout This Manual Notational Conventionsasect ªsection nameº, address LALK 16±bit constant , shiftbyte value1 , ... , valuen C csr ±a /user/ti/simuboard/utilitiesPCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046 OHCI.Lynx Configuration Information Application Report, SLLA077TSB41LV03A Data Sheet, SLLS364 Related Documentation From Texas InstrumentsPage Contents A Global Reset Only Bits, PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Figures 1±1 Typical System Architecture 1±2 Serialized Interrupt Signal1±3 EEPROM 2-Wire Interface 1±4 TPS22X6 Power Switch Interface 1±5 Example of a ZV Interface 1±6 Distributed DMA Signal ConnectionTables PCI445X Device ChapterPage TopicFigure 1±1. Typical System Architecture 1.1 System Features Selection 1.1.3 PME and RI Signaling1.1.1 Package Types 1.1.2 GRST and PRST1.1.7 Socket Power Switches 1.1.9 Optional PCI Signals1.1.6 PCI and ISA Style Interrupt 1.1.8 Distributed DMA DDMAFigure 1±2. Serialized Interrupt Signal 1.1.10 Socket Activity LEDs1.1.11 MFUNC7±MFUNC0 Terminal Assignments 1.1.12 Miscellaneous Functions Description1.1.12.4 CardBus Reserved Terminal Signaling 1.1.12.6 Power Savings Mode1.1.12.3 Asynchronous CSC Interrupt Generation 1.1.12.5 Memory Burst R/W Operation Control1.1.12.10 Socket Power Lock 1.1.12.9 SMI1.1.12.11VCC Protection 1.1.12.12 ZV Port Control and Auto Detect Function1.2 System Implementation 1.2.1 Clamping Rails1.2.2 PCI Bus Interface PCLK, AD31±AD0, C/BE3±C/BE0, PAR, DEVSEL, FRAME, STOPPRST PCI reset and GRST Global reset INTA, INTB, and INTCCLKRUN Note Pullup Resistor Requirements1.2.4 2-Wire I2C Interface for EEPROM Figure 1±3. EEPROM 2-Wire InterfaceSocket power supply 1.2.3 PC Card InterfaceTable 1±1. Registers and Bits Loadable Through Serial EEPROM Register OffsetRegister Bits Loaded From1.3 Sample PCI445X EEPROM Data File Following is an example EEPROM data file used with the PCI445X device1D 0xFF 1E 0xFF 1F 0xFF 1.3.1 P2C Interface for TPS22X6 Power Switch Figure 1±4. TPS22X6 Power Switch Interface1.3.2 Zoomed Video ZV Interface Figure 1±5. Example of a ZV Interface1.3.3 Interrupt Signaling Interface 1.3.4 Miscellaneous SignalsSerialized Interrupt Interface Parallel PCI InterruptFigure 1±6. Distributed DMA Signal Connection 1.3.5 Requirement of Pullup/Pulldown ResistorsTable 1±2. PC Card Interface Pullup Resistor List² ³ System ImplementationTable 1±3. PCI Bus Interface Pullup Resistor List Table 1±4. Miscellaneous Terminals Pullup Resistor ListTable 1±5. Required Pullup/Pulldown Resistors SignalPulldown Default System Implementation1.4 BIOS Considerations Command register PCI offset 04h 16-bitLatency timer PCI offset 0Dh 8-bit CardBus latency timer register PCI offset 1Bh 8-bitPower management control/status register PCI offset A4h 16-bit 1.4.2 System Sleeping State Consideration1.4.1.2 PCI TI Proprietary Registers Initialization 1 SUSPEND2 Register save/restore 1.4.3 Docking System Consideration1.5.4 Socket Power Control 1.5 Important Information1.5.1 GRST Clamping Rail 1.5.2 PME/RIOUT Bit DefinitionAppendix A TopicGlobal Reset Only Bits, PME Context Bits PageA.1 Global Reset Only Bits/PME Context Bits Table A±1.Global Reset Only Cleared BitsTable A±2.PME Context Bits Page PME and RI Behavior Appendix BTopic PageTable B±1.CardBus CTSCHG and Wake-Up Signals Truth Table Table B±2.16-Bit Card RI/STSCHG and Wake-Up Signals Truth TableB.1 PME and RI Behavior PCI445X Buffer Types Appendix CTopic PagePCI445X Buffer Types Table C±1. PCI445X Terminal Function Assignment and Buffer TypesPCI445X Buffer Types Signal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalSignal Name Signal NamePCI445X Buffer Types TerminalTable C±2. Buffer Type Abbreviations PCI445X Buffer TypesBuffer Type Description