Texas Instruments PCI445X manual System Features Selection

System Features Selection

1.1 System Features Selection

This section explains selectable system features. Feature selection is required for GPIO and MFUNC terminal assignments and PCI445X register initialization. Detailed system implementation methods are described in the following sections. All functions cannot necessarily be used at the same time, because of the limitations of programmable multifunction terminals (i.e., MFUNC7±MFUNC0).

1.1.1Package Types

The Texas Instruments PCI445X device is offered in two package types: 256-terminal ball grid array (BGA) and 257-terminal MicroStar BGA . MicroStar BGA is a type of chip scale packaging (CSP).

1.1.2G_RST and PRST

The PCI445X device has two reset inputs, G_RST and PRST. G_RST resets all registers and state-machines; PRST resets registers that are not required to maintain context in a low power state (see Table A±1 and Table A±2). If the system does not support a wake-up event from D3-state (hot or cold), then these terminals can be tied together.

1.1.3PME and RI Signaling

For supporting a wake-up event, a power management event (PME) and/or an RI signal should be signaled to the system. PME is available only on the RI_OUT/PME terminal. RI_OUT is available on RI_OUT/PME or MFUNC7. PME and RI_OUT signals are usually connected to the south bridge or embedded controller (EC). Detailed PME and RI signal behavior is explained later.

1.1.4ZV Support

The PCI445X device has internal zoomed video (ZV) buffers. It can support three ZV sources, from two PC cards and one external source. Refer to the detailed implementation guide in Section 1.3.2. The PCI445X device has the ZV autodetect function for supporting a third external zoomed video source. ZVSTAT and ZVPCLK are required to support the third source. (The ZV autodetect function needs ZVPCLK for input, and ZVSTAT for enabling.) ZVSTAT can be assigned on the MFUNC0, MFUNC1, or MFUNC4 terminal.

1.1.5EEPROM for Subsystem Vendor and Subsystem ID Registers

Subsystem vendor ID and subsystem ID registers (PCI offsets 40h and 42h) can be loaded from EEPROM through a two-wire serial interface. These registers can be configured by BIOS if the PCI445X device is implemented on the motherboard, by setting the SUBSYSRW bit (system control register, PCI offset 80h, bit 5). EEPROM may be required for docking systems and is required for add-in cards. The EEPROM interface terminals SDA and SCL are

PCI445X Device 1-3