Global Reset Only Bits/PME Context Bits
A.1 Global Reset Only Bits/PME Context Bits
Table A±1.Global Reset Only Cleared Bits
| Register Name | Space | Offset | Bit | |
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| Subsystem IDs | PCI | 40h | 31±0 | |
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| PC card | PCI | 44h | 31±1 | |
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| System control | PCI | 80h | 31±29, 27±24, 22±14, 6±3, | |
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| 1±0 |
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| Multimedia control | PCI | 84h | 7±0 | |
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| General status | PCI | 85h | 2±0 | |
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| GPIO0 control | PCI | 88h | 7, 6, 4, 3, 1, 0 | |
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| GPIO1 control | PCI | 89h | 7, 6, 3, 1, 0 | |
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| GPIO2 control | PCI | 8Ah | 7, 6, 4, 3, 1, 0 | |
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| GPIO3 control | PCI | 8Bh | 7, 6, 3, 1, 0 | |
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| MFUNC routing | PCI | 8Ch | 31±0 | |
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| Retry status | PCI | 90h | 7±1 | |
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| Card control | PCI | 91h | 7, 6, 2, 1, 0 | |
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| Device control | PCI | 92h | 7±0 | |
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| Diagnostic | PCI | 93h | 7±0 | |
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| Socket DMA register 0 | PCI | 94h | 1±0 | |
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| Socket DMA register 1 | PCI | 98h | 15±0 | |
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| control/status | PCI | A8h | 10, 9, 8, 2, 1, 0 |
| GPE | ||||
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Note: The following link registers are reset by global reset only.
PCI subsystem identification registerÐPCI offset 2Ch
MIN_GNT and MAX_LAT registerÐPCI offset 3Eh
PCI OHCI control registerÐPCI offset 40h
Power management control and status registerÐPCI offset 48h
PCI miscellaneous and configuration registerÐPCI offset F0h
Link enhancement control registerÐPCI offset F4h
However, there is no support in the OS for the
