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Texas Instruments PCI445X manual ±3. PCI Bus Interface Pullup Resistor List

Models: PCI445X

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System Implementation

Table 1±3. PCI Bus Interface Pullup Resistor List

PCI Signal

Pull-Up Voltage

VCCP

FRAME

VCCP

TRDY

VCCP

IRDY

VCCP

DEVSEL

VCCP

STOP

VCCP

SERR

VCCP

PERR

VCCP

LOCK

INTA

INTB

VCCP

INTC

VCCP

CLKRUN

VCCP

PRST

VCCP

G_RST

System dependent

PME

The pullup/pulldown on MFUNC depends on how it is implemented. Some signals may require pullups, others pulldowns, and for a GPI or GPO only the system designer would know how that line should be pulled.

Table 1±4. Miscellaneous Terminals Pullup Resistor List

PCI Signal	Required Situation	Pullup/Pulldown
		Voltage

MFUNC7±MFUNC4	N/C or used as output	VCCP or GND

MFUNC3±MFUNC0	N/C or used as output	VCCP or GND
(GPIO3±GPIO0)


MFUNC7(LOCK)	N/C or used as output	VCCP
CLOCK	Internal OSC is selected	GND

LATCH	If MFUNC7 is used for IDSEL	GND

IRQSER		VCCP
		System dependent
RI_OUT/PME		System dependent

		System dependent
SUSPEND		System dependent

Note: Removing clamping voltage makes all the clamped signals low.

PCI445X Device

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Texas Instruments PCI445X ±3. PCI Bus Interface Pullup Resistor List, ±4. Miscellaneous Terminals Pullup Resistor List

Contents

SCPU007 PCI Bus SolutionsImplementation Guide AugustIMPORTANT NOTICE Notational Conventions How to Use This ManualRead This First About This ManualC csr ±a /user/ti/simuboard/utilities asect ªsection nameº, addressLALK 16±bit constant , shift byte value1 , ... , valuenRelated Documentation From Texas Instruments PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046OHCI.Lynx Configuration Information Application Report, SLLA077 TSB41LV03A Data Sheet, SLLS364Page Contents A Global Reset Only Bits, PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 1±5 Example of a ZV Interface 1±6 Distributed DMA Signal Connection Figures1±1 Typical System Architecture 1±2 Serialized Interrupt Signal 1±3 EEPROM 2-Wire Interface 1±4 TPS22X6 Power Switch InterfaceTables Topic PCI445X DeviceChapter PageFigure 1±1. Typical System Architecture 1.1.2 GRST and PRST 1.1 System Features Selection1.1.3 PME and RI Signaling 1.1.1 Package Types1.1.8 Distributed DMA DDMA 1.1.7 Socket Power Switches1.1.9 Optional PCI Signals 1.1.6 PCI and ISA Style Interrupt1.1.12 Miscellaneous Functions Description Figure 1±2. Serialized Interrupt Signal1.1.10 Socket Activity LEDs 1.1.11 MFUNC7±MFUNC0 Terminal Assignments1.1.12.5 Memory Burst R/W Operation Control 1.1.12.4 CardBus Reserved Terminal Signaling1.1.12.6 Power Savings Mode 1.1.12.3 Asynchronous CSC Interrupt Generation1.1.12.12 ZV Port Control and Auto Detect Function 1.1.12.10 Socket Power Lock1.1.12.9 SMI 1.1.12.11VCC ProtectionPCLK, AD31±AD0, C/BE3±C/BE0, PAR, DEVSEL, FRAME, STOP 1.2 System Implementation1.2.1 Clamping Rails 1.2.2 PCI Bus InterfaceNote Pullup Resistor Requirements PRST PCI reset and GRST Global resetINTA, INTB, and INTC CLKRUN1.2.3 PC Card Interface 1.2.4 2-Wire I2C Interface for EEPROMFigure 1±3. EEPROM 2-Wire Interface Socket power supplyBits Loaded From Table 1±1. Registers and Bits Loadable Through Serial EEPROMRegister Offset RegisterFollowing is an example EEPROM data file used with the PCI445X device 1.3 Sample PCI445X EEPROM Data File1D 0xFF 1E 0xFF 1F 0xFF Figure 1±5. Example of a ZV Interface 1.3.1 P2C Interface for TPS22X6 Power SwitchFigure 1±4. TPS22X6 Power Switch Interface 1.3.2 Zoomed Video ZV InterfaceParallel PCI Interrupt 1.3.3 Interrupt Signaling Interface1.3.4 Miscellaneous Signals Serialized Interrupt InterfaceSystem Implementation Figure 1±6. Distributed DMA Signal Connection1.3.5 Requirement of Pullup/Pulldown Resistors Table 1±2. PC Card Interface Pullup Resistor List² ³Table 1±4. Miscellaneous Terminals Pullup Resistor List Table 1±3. PCI Bus Interface Pullup Resistor ListSystem Implementation Table 1±5. Required Pullup/Pulldown ResistorsSignal Pulldown DefaultCardBus latency timer register PCI offset 1Bh 8-bit 1.4 BIOS ConsiderationsCommand register PCI offset 04h 16-bit Latency timer PCI offset 0Dh 8-bit1 SUSPEND Power management control/status register PCI offset A4h 16-bit1.4.2 System Sleeping State Consideration 1.4.1.2 PCI TI Proprietary Registers Initialization1.4.3 Docking System Consideration 2 Register save/restore1.5.2 PME/RIOUT Bit Definition 1.5.4 Socket Power Control1.5 Important Information 1.5.1 GRST Clamping RailPage Appendix ATopic Global Reset Only Bits, PME Context BitsTable A±1.Global Reset Only Cleared Bits A.1 Global Reset Only Bits/PME Context BitsTable A±2.PME Context Bits Page Page PME and RI BehaviorAppendix B TopicTable B±1.CardBus CTSCHG and Wake-Up Signals Truth Table Table B±2.16-Bit Card RI/STSCHG and Wake-Up Signals Truth TableB.1 PME and RI Behavior Page PCI445X Buffer TypesAppendix C TopicPCI445X Buffer Types Table C±1. PCI445X Terminal Function Assignment and Buffer TypesPCI445X Buffer Types Terminal Signal NameSignal Name PCI445X Buffer TypesTerminal Signal NameSignal Name PCI445X Buffer TypesTerminal Signal NameSignal Name PCI445X Buffer TypesTerminal Signal NameSignal Name PCI445X Buffer TypesDescription Table C±2. Buffer Type AbbreviationsPCI445X Buffer Types Buffer Type