Global Reset Only Bits/PME Context Bits
Table A±2.PME Context Bits
Register Name | Space | Offset | Bit |
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Bridge control | PCI | 3Eh | 6 |
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Power management capabilities | PCI | A2h | 15 |
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Power management control/status | PCI | A4h | 15, 8 |
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ExCA power control | ExCA | 802h, 842h | 4, 3, 1, 0 |
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ExCA interrupt and general control | ExCA | 803h/843h | 6 |
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ExCA card status change | ExCA | 804h/844h | 3, 2, 1, 0 |
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ExCA card status change interrupt | ExCA | 805h/845h | 3, 2, 1, 0 |
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CardBus socket event | CardBus | 00h | 3, 2, 1, 0 |
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CardBus socket mask | CardBus | 04h | 3, 2, 1, 0 |
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CardBus socket status | CardBus | 10h | 6, 5, 4, 2, 1, 0 |
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Global reset only bits are cleared (to default value) only when G_RST is asserted.
PME context bits are not cleared (to default value) by PRST if the PME_EN bit is set to 1.
Both G_RST and PRST can be gated by asserting the SUSPEND signal.
Global Reset Only Bits, PME Context Bits |
