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Texas Instruments PCI445X manual B.1 PME and RI Behavior

Models: PCI445X

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B.1 PME and RI Behavior

B.1 PME and RI Behavior

Table B±1.CardBus CTSCHG and Wake-Up Signals Truth Table


RINGEN	RIMUX	RIENB	PME_EN	PME_STAT	RI_OUT/PME					MFUNC7

0	0	0	0	Latched	±±±					±±±

0	0	0	1	Latched	Latched CSTSCHG					±±±

0	0	1	0	Latched	±±±					±±±

0	0	1	1	Latched	±±±					±±±

0	1	0	0	Latched	±±±					±±±

0	1	0	1	Latched	Latched CSTSCHG					±±±

0	1	1	0	Latched	±±±					±±±

0	1	1	1	Latched	Latched CSTSCHG					±±±

1	0	0	0	Latched	±±±					±±±

1	0	0	1	Latched	Latched CSTSCHG					±±±

1	0	1	0	Latched	CSTSCHG					CSTSCHG

1	0	1	1	Latched	CSTSCHG					CSTSCHG

1	1	0	0	Latched	±±±					±±±

1	1	0	1	Latched	Latched CSTSCHG					±±±

1	1	1	0	Latched	±±±					CSTSCHG

1	1	1	1	Latched	Latched CSTSCHG					CSTSCHG

Table B±2.16-Bit Card RI/STSCHG and Wake-Up Signals Truth Table


RINGEN	RIMUX	RIENB	PME_EN	PME_STAT	RI_OUT/PME					MFUNC7

0	±±±	±±±	±±±	±±±	±±±					±±±

1	0	0	0	Latched	±±±					±±±

1	0	0	1	Latched	Latched RI					±±±

1	0	1	0	Latched	RI					RI

1	0	1	1	Latched	RI					RI

1	1	0	0	Latched	±±±					±±±

1	1	0	1	Latched	Latched RI					±±±

1	1	1	0	Latched	±±±					RI

1	1	1	1	Latched	Latched RI					RI

B-2

Image 38

Texas Instruments PCI445X manual B.1 PME and RI Behavior, Table B±1.CardBus CTSCHG and Wake-Up Signals Truth Table

Contents

August PCI Bus SolutionsImplementation Guide SCPU007IMPORTANT NOTICE About This Manual How to Use This ManualRead This First Notational Conventionsbyte value1 , ... , valuen asect ªsection nameº, addressLALK 16±bit constant , shift C csr ±a /user/ti/simuboard/utilitiesTSB41LV03A Data Sheet, SLLS364 PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046OHCI.Lynx Configuration Information Application Report, SLLA077 Related Documentation From Texas InstrumentsPage Contents A Global Reset Only Bits, PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 1±3 EEPROM 2-Wire Interface 1±4 TPS22X6 Power Switch Interface Figures1±1 Typical System Architecture 1±2 Serialized Interrupt Signal 1±5 Example of a ZV Interface 1±6 Distributed DMA Signal ConnectionTables Page PCI445X DeviceChapter TopicFigure 1±1. Typical System Architecture 1.1.1 Package Types 1.1 System Features Selection1.1.3 PME and RI Signaling 1.1.2 GRST and PRST1.1.6 PCI and ISA Style Interrupt 1.1.7 Socket Power Switches1.1.9 Optional PCI Signals 1.1.8 Distributed DMA DDMA1.1.11 MFUNC7±MFUNC0 Terminal Assignments Figure 1±2. Serialized Interrupt Signal1.1.10 Socket Activity LEDs 1.1.12 Miscellaneous Functions Description1.1.12.3 Asynchronous CSC Interrupt Generation 1.1.12.4 CardBus Reserved Terminal Signaling1.1.12.6 Power Savings Mode 1.1.12.5 Memory Burst R/W Operation Control1.1.12.11VCC Protection 1.1.12.10 Socket Power Lock1.1.12.9 SMI 1.1.12.12 ZV Port Control and Auto Detect Function1.2.2 PCI Bus Interface 1.2 System Implementation1.2.1 Clamping Rails PCLK, AD31±AD0, C/BE3±C/BE0, PAR, DEVSEL, FRAME, STOPCLKRUN PRST PCI reset and GRST Global resetINTA, INTB, and INTC Note Pullup Resistor RequirementsSocket power supply 1.2.4 2-Wire I2C Interface for EEPROMFigure 1±3. EEPROM 2-Wire Interface 1.2.3 PC Card InterfaceRegister Table 1±1. Registers and Bits Loadable Through Serial EEPROMRegister Offset Bits Loaded From1.3 Sample PCI445X EEPROM Data File Following is an example EEPROM data file used with the PCI445X device1D 0xFF 1E 0xFF 1F 0xFF 1.3.2 Zoomed Video ZV Interface 1.3.1 P2C Interface for TPS22X6 Power SwitchFigure 1±4. TPS22X6 Power Switch Interface Figure 1±5. Example of a ZV InterfaceSerialized Interrupt Interface 1.3.3 Interrupt Signaling Interface1.3.4 Miscellaneous Signals Parallel PCI InterruptTable 1±2. PC Card Interface Pullup Resistor List² ³ Figure 1±6. Distributed DMA Signal Connection1.3.5 Requirement of Pullup/Pulldown Resistors System ImplementationTable 1±3. PCI Bus Interface Pullup Resistor List Table 1±4. Miscellaneous Terminals Pullup Resistor ListPulldown Default Table 1±5. Required Pullup/Pulldown ResistorsSignal System ImplementationLatency timer PCI offset 0Dh 8-bit 1.4 BIOS ConsiderationsCommand register PCI offset 04h 16-bit CardBus latency timer register PCI offset 1Bh 8-bit1.4.1.2 PCI TI Proprietary Registers Initialization Power management control/status register PCI offset A4h 16-bit1.4.2 System Sleeping State Consideration 1 SUSPEND2 Register save/restore 1.4.3 Docking System Consideration1.5.1 GRST Clamping Rail 1.5.4 Socket Power Control1.5 Important Information 1.5.2 PME/RIOUT Bit DefinitionGlobal Reset Only Bits, PME Context Bits Appendix ATopic PageA.1 Global Reset Only Bits/PME Context Bits Table A±1.Global Reset Only Cleared BitsTable A±2.PME Context Bits Page Topic PME and RI BehaviorAppendix B PageB.1 PME and RI Behavior Table B±1.CardBus CTSCHG and Wake-Up Signals Truth TableTable B±2.16-Bit Card RI/STSCHG and Wake-Up Signals Truth Table Topic PCI445X Buffer TypesAppendix C PagePCI445X Buffer Types PCI445X Buffer TypesTable C±1. PCI445X Terminal Function Assignment and Buffer Types PCI445X Buffer Types Signal NameSignal Name TerminalPCI445X Buffer Types Signal NameSignal Name TerminalPCI445X Buffer Types Signal NameSignal Name TerminalPCI445X Buffer Types Signal NameSignal Name TerminalBuffer Type Table C±2. Buffer Type AbbreviationsPCI445X Buffer Types Description