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Texas Instruments TAS3002 manual Address, Byte Number, Function, TAS3001

Models: TAS3002

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Table 7−3. 512-Byte EEPROM Memory Map 2.1 Channels (with TAS3001)

	ADDRESS	BYTE NUMBER	FUNCTION

	000h	1	Signature (2Ah)

	001h	1	ID byte = 0000 0011

			TAS3002

	002h	1	MCR

	003h−00Bh	9	Mixer left gain

	00Ch−014h	9	Mixer right gain

	015h−01Ah	6	DRC (ratio, threshold, energyα, attackα, decayα)

	01Bh	1	Bass

	01Ch	1	Treble

	01Dh−022h	6	Volume

	031h−03Fh	15	Biquad 0

	040h−04Eh	15	Biquad 1

	04Fh−05Dh	15	Biquad 2	TAS3002
				TAS3002
	05Eh−06Ch	15	Biquad 3	right and left
				channel
	06Dh−07Bh	15	Biquad 4	channel
	06Dh−07Bh	15	Biquad 4

	07Ch−08Ah	15	Biquad 5

	08Bh−099h	15	Biquad 6

	09Ah	1	0 dB/bass

	09Bh	1	0 dB/treble

	09Ch−0A1h	6	Bass break

	0A2h−0A7h	6	Treble break

	0A8h−110h	105	Bass delta

	111h−179h	105	Treble delta

	17Ah−17Fh	6	Bass set point

	180h−185h	6	Treble set point

	186h−194h	15	Biquad 0

	195h−1A3h	15	Biquad 1

	1A4h−1B2h	15	Biquad 2	TAS3001
				TAS3001
	1B3h−1C1h	15	Biquad 3	right and left
				channel
	1C2h−1D0h	15	Biquad 4	channel
	1C2h−1D0h	15	Biquad 4

	1D1h−1DFh	15	Biquad 5

	1E0h−1EEh	15	Biquad 6

			TAS3001

	1EFh	1	MCR

	1F0h−1F2h	3	SDIN1 gain

	1F3h−1F5h	3	SDIN2 gain

	1F6h−1F7h	2	DRC (ratio, threshold, energyα, attackα, decayα)

	1F8h	1	Bass

	1F9h	1	Treble

	1FAh−1FFh	6	Volume

NOTE: In this mode, the TAS3002 and the TAS3001 devices both use the same equalization coefficients for their right and left channels. Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.

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Image 42

Texas Instruments TAS3002 manual Address, Byte Number, Function, TAS3001

Contents

Digital Audio Processor With Codec Data ManualTAS3002 2001IMPORTANT NOTICE 1.2Features 1 Introduction1.1 Description 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram Figure 1−2. TAS3002 Terminal Assignments 1.4 Terminal Assignments1.5 Terminal Functions Table 1−1. TAS3002 Terminal FunctionsTable 1−1. TAS3002 Terminal Functions Continued Page 2 Audio Data Formats 2.1 Serial Interface FormatsTable 2−1. Serial Interface Options … … … … … … … …2.2 Digital Output Modes … … … …… … … … 2.2.2I2S Serial-InterfaceFormatFigure 2−2. I 2S Serial-InterfaceFormat … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …UNIT 2.3 Switching CharacteristicsPARAMETER tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0Page 3.2 Analog Output 3 Analog Input/Output3.1 Analog Input 3.2.1Direct Analog Output3.2.2Analog Output With Gain Figure 3−2. VCOM Decoupling NetworkFigure 3−3. Analog Output With External Amplifier 3.2.3Reference Voltage Filter TAS3002Figure 3−4. TAS3002 Reference Voltage Filter Page 4.2 Software Soft Mute 4.1 Soft Volume Update4 Audio Control/Enhancement Functions 4.3 Input Mixer Control4.4 Mono Mixer Control 4.5 Treble ControlFigure 4−1. TAS3002 Mixer Function 4.6 Bass Control 4.7 De-EmphasisMode DMFigure 4−2. De-EmphasisMode Frequency Response 4.8 Analog Control Register 40h Table 4−1. Analog Control Register Description4.9.2Loudness Gain 4.9 Dynamic Loudness Contour4.9.1Loudness Biquads 4.9.3Loudness Contour Operation4.10 Dynamic Range Compression/Expansion DRCE 4.11 AllPass FunctionTable 4−2. Main Control Register 1 Description 4.12 Main Control Register 1 01h4.13 Main Control Register 2 43h Table 4−3. Main Control Register 2 DescriptionPage 5.1 Biquad Block Figure 5−1. Biquad Cascade Configuration5 Filter Processor 5.1.1Filter CoefficientsPage 6.2 I2C Protocol 6 I2C Serial Control Interface6.1 Introduction Figure 6−1. Typical I 2C Data Transfer SequenceTable 6−1. I 2C Protocol Definitions 6.3 Operation6.3.1Write Cycle Example Table 6−2. I 2C Address Byte Table6.3.2TAS3002 I2C Readback Example 6.3.3I2C Wait States6.4.2Write Byte Protocol 6.4 SMBus Operation6.4.1Block Write Protocol Table 6−3. I 2C Wait States6.4.3Wait States 6.4.4TAS3002 SMBus ReadbackPage 7.2.2Reset 7.2 Power-Up/Power-DownReset7.2.1Power-UpSequence 7 Microcontroller Operation7.2.4Fast Load Mode 7.2.3Reset CircuitFigure 7−1. TAS3002 Reset Circuit TAS30027.3 Power-DownMode 7.2.5Codec Reset7.4 Test Mode 7.3.1Power-DownTiming SequenceFigure 7−2. Power-DownTiming Sequence 7.5 Internal Interface7.6.2GPI Architecture Table 7−1. GPI Terminal ProgrammingStart Power Up Initialize Default EEPROM Figure 7−3. Internal Interface Flow ChartRestore Volume and MCR Slave Write GPI Power Down7.7 External EEPROM Memory Maps Table 7−2. 512-ByteEEPROM Memory Map 2.0 ChannelsFUNCTION ADDRESSBYTE NUMBER TAS3002FUNCTION TAS3002 ADDRESSNUMBER CATEGORYFUNCTION TAS3002 ADDRESSNUMBER CATEGORY8 Electrical Characteristics Static Digital Specifications8.2 Recommended Operating Conditions Figure 8−1. ADC Digital Filter Characteristics 8.4 ADC Digital FilterFigure 8−4. ADC High-PassFilter Characteristics 8.5 Analog-to-DigitalConverter8.6 Input Multiplexer 8.7 DAC Interpolation Filter8.8 Digital-to-AnalogConverter 8.9 DAC Output Performance Data8.10 I2C Serial Port Timing Characteristics Figure 8−7. I 2C Bus TimingTAS3002 9 System DiagramsFigure 9−1. Stereo Application ClockTAS3001 Figure 9−2. TAS3002 Device, 2.1 ChannelsTAS3002 10 Mechanical Information PFB S-PQFP-G48PLASTIC QUAD FLATPACK 10−2