Texas Instruments TAS3002 manual 8.10 I2C Serial Port Timing Characteristics, 7. I 2C Bus Timing

8.10 I2C Serial Port Timing Characteristics

		MIN	MAX	UNIT
f(SCL)	SCL clock frequency	0	100	kHz
t(buf)	Bus free time between start and stop	4.7		∝s
t(low)	Low period of SCL clock	4.7		∝s
t(high)	High period of SCL clock	4.0		∝s
th(sta)	Hold time repeated start	4.0		∝s
tsu(sta)	Setup time repeated start	4.7	20	∝s
th(dat)	Data hold time (See Note 6)	0		∝s
tsu(dat)	Data setup time	250		ns
tr	Rise time for SDA and SCL		1000	ns
tf	Fall time for SDA and SCL		300	ns
tsu(sto)	Setup time for stop condition	4.0		∝s
C(b)	Capacitive load for each bus line		400	pF

NOTE 6: A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.

P SP

SDA	Valid
t(buf)	th(dat)

trtsu(dat)

	Change
	of Data
SCL	Allowed

Data

Line

Stable

tf

th(sta)

NOTE: t(low) is measured from the end of tf to the beginning of tr. t(high) is measured from the end of tr to the beginning of tf.

tsu(sta)

tsu(sto)

th(sta)

Figure 8−7. I 2C Bus Timing

8−6