System Diagrams, 1. Stereo Application | Texas Instruments TAS3002

9 System Diagrams

Figure 9−1 and Figure 9−2 show the TAS3002 stereo and 2.1-channel applications, respectively.

SPDIF

USB

Analog In

I2S

+3.3 VDD

RESET

Select Logic
Clock	TAS3002
	TAS3002

Analog Out

EEPROM

I2C

Master

B-T-V-EQ Switches

NOTE: Items such as the PLL network and power supplies are omitted for clarity.

Figure 9−1. Stereo Application

9−1

Page 51

Image 51

Texas Instruments TAS3002 manual System Diagrams, 1. Stereo Application, Clock

Contents

2001 Data ManualTAS3002 Digital Audio Processor With Codec IMPORTANT NOTICE 1.2Features 1 Introduction1.1 Description 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram Table 1−1. TAS3002 Terminal Functions 1.4 Terminal Assignments1.5 Terminal Functions Figure 1−2. TAS3002 Terminal Assignments Table 1−1. TAS3002 Terminal Functions Continued Page 2 Audio Data Formats 2.1 Serial Interface FormatsTable 2−1. Serial Interface Options … … … … … … … …2.2 Digital Output Modes … … … … … … … … 2.2.2I2S Serial-InterfaceFormatFigure 2−2. I 2S Serial-InterfaceFormat … … … … … … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … … tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0 2.3 Switching CharacteristicsPARAMETER UNITPage 3.2.1Direct Analog Output 3 Analog Input/Output3.1 Analog Input 3.2 Analog Output 3.2.2Analog Output With Gain Figure 3−2. VCOM Decoupling NetworkFigure 3−3. Analog Output With External Amplifier 3.2.3Reference Voltage Filter TAS3002Figure 3−4. TAS3002 Reference Voltage Filter Page 4.3 Input Mixer Control 4.1 Soft Volume Update4 Audio Control/Enhancement Functions 4.2 Software Soft Mute 4.4 Mono Mixer Control 4.5 Treble ControlFigure 4−1. TAS3002 Mixer Function 4.6 Bass Control 4.7 De-EmphasisMode DMFigure 4−2. De-EmphasisMode Frequency Response Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h 4.9.3Loudness Contour Operation 4.9 Dynamic Loudness Contour4.9.1Loudness Biquads 4.9.2Loudness Gain 4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCE Table 4−3. Main Control Register 2 Description 4.12 Main Control Register 1 01h4.13 Main Control Register 2 43h Table 4−2. Main Control Register 1 DescriptionPage 5.1.1Filter Coefficients Figure 5−1. Biquad Cascade Configuration5 Filter Processor 5.1 Biquad BlockPage Figure 6−1. Typical I 2C Data Transfer Sequence 6 I2C Serial Control Interface6.1 Introduction 6.2 I2C Protocol Table 6−2. I 2C Address Byte Table 6.3 Operation6.3.1Write Cycle Example Table 6−1. I 2C Protocol Definitions 6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback Example Table 6−3. I 2C Wait States 6.4 SMBus Operation6.4.1Block Write Protocol 6.4.2Write Byte Protocol 6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7 Microcontroller Operation 7.2 Power-Up/Power-DownReset7.2.1Power-UpSequence 7.2.2Reset TAS3002 7.2.3Reset CircuitFigure 7−1. TAS3002 Reset Circuit 7.2.4Fast Load Mode 7.2.5Codec Reset 7.3 Power-DownMode 7.5 Internal Interface 7.3.1Power-DownTiming SequenceFigure 7−2. Power-DownTiming Sequence 7.4 Test Mode Table 7−1. GPI Terminal Programming 7.6.2GPI Architecture Slave Write GPI Power Down Figure 7−3. Internal Interface Flow ChartRestore Volume and MCR Start Power Up Initialize Default EEPROM Table 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory Maps TAS3002 ADDRESSBYTE NUMBER FUNCTION CATEGORY TAS3002 ADDRESSNUMBER FUNCTION CATEGORY TAS3002 ADDRESSNUMBER FUNCTION 8 Electrical Characteristics Static Digital Specifications8.2 Recommended Operating Conditions 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics 8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics 8.7 DAC Interpolation Filter 8.6 Input Multiplexer 8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverter Figure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing Characteristics Clock 9 System DiagramsFigure 9−1. Stereo Application TAS3002 TAS3001 Figure 9−2. TAS3002 Device, 2.1 ChannelsTAS3002 10 Mechanical Information PFB S-PQFP-G48PLASTIC QUAD FLATPACK 10−2