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Texas Instruments TAS3002 SMBus Operation, 6.4.1Block Write Protocol, 6.4.2Write Byte Protocol

Models: TAS3002

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Table 6−3 gives typical values of the wait states that can be expected with the various functions of the part:

Table 6−3. I 2C Wait States

	SYSTEM SAMPLING FREQUENCY
				Comment
	32 kHz	44.1 kHz	48 kHz	Comment

Volume	62 ms	49 ms	41 ms	Not dependent on size of change

Bass	231 ms	167 ms	153 ms	0 to −18 dB

Treble	231 ms	167 ms	153 ms	0 to −18 dB

DRC on	300 ∝s	300 ∝s	300 ∝s

Mixer	None	None	None

Loudness	None	None	None

Equalization	15 ms	190 ∝s	300 ∝s	Can occur with each filter

6.4 SMBus Operation

The TAS3002 device supports a subset of the SMBus protocol. With proper programming techniques, it is possible to use the SMBus to set up the TAS3002 device.

6.4.1Block Write Protocol

The TAS3002 device supports the block write protocol that allows up to 32 bytes to be sent as a block. To send a command using this format, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be programmed into the SMBus command byte. This operation signals the TAS3002 device that the next byte is the SMBus byte-count byte. The next byte after the byte count is then entered into the device as the first byte of data.

SMBus

Command Byte

68h	8rh	xx	dd	dd	dd
TAS3002	Subaddress	Byte Count	Data	Data	Data
Address	(r = subaddress)	(Don’t Care)

6.4.2Write Byte Protocol

The TAS3002 device also supports the SMBus write byte protocol. Writing to the main control register (MCR), bass, and treble registers requires using the byte write protocol. To send a command using this protocol, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be programmed into the SMBus command byte. The next byte after the command byte is then entered into the device as the first byte of data.

SMBus

Command Byte

68h	8rh	dd

TAS3002	Subaddress	Data
Address	(r = subaddress)

6−4

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Texas Instruments TAS3002 manual SMBus Operation, 6.4.1Block Write Protocol, 6.4.2Write Byte Protocol, 3. I 2C Wait States

Contents

Data Manual TAS3002Digital Audio Processor With Codec 2001IMPORTANT NOTICE 1.1 Description 1.2Features1 Introduction 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram 1.4 Terminal Assignments 1.5 Terminal FunctionsFigure 1−2. TAS3002 Terminal Assignments Table 1−1. TAS3002 Terminal FunctionsTable 1−1. TAS3002 Terminal Functions Continued Page Table 2−1. Serial Interface Options 2 Audio Data Formats2.1 Serial Interface Formats … … … … 2.2 Digital Output Modes… … … … … … … …2.2.2I2S Serial-InterfaceFormat Figure 2−2. I 2S Serial-InterfaceFormat… … … … … … … …2.2.3MSB-Left-Justified, Serial-InterfaceFormat … … … …… … … … … … … …2.3 Switching Characteristics PARAMETERUNIT tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0Page 3 Analog Input/Output 3.1 Analog Input3.2 Analog Output 3.2.1Direct Analog OutputFigure 3−3. Analog Output With External Amplifier 3.2.2Analog Output With GainFigure 3−2. VCOM Decoupling Network Figure 3−4. TAS3002 Reference Voltage Filter 3.2.3Reference Voltage FilterTAS3002 Page 4.1 Soft Volume Update 4 Audio Control/Enhancement Functions4.2 Software Soft Mute 4.3 Input Mixer ControlFigure 4−1. TAS3002 Mixer Function 4.4 Mono Mixer Control4.5 Treble Control Figure 4−2. De-EmphasisMode Frequency Response 4.6 Bass Control4.7 De-EmphasisMode DM 4.8 Analog Control Register 40h Table 4−1. Analog Control Register Description4.9 Dynamic Loudness Contour 4.9.1Loudness Biquads4.9.2Loudness Gain 4.9.3Loudness Contour Operation4.10 Dynamic Range Compression/Expansion DRCE 4.11 AllPass Function4.12 Main Control Register 1 01h 4.13 Main Control Register 2 43hTable 4−2. Main Control Register 1 Description Table 4−3. Main Control Register 2 DescriptionPage Figure 5−1. Biquad Cascade Configuration 5 Filter Processor5.1 Biquad Block 5.1.1Filter CoefficientsPage 6 I2C Serial Control Interface 6.1 Introduction6.2 I2C Protocol Figure 6−1. Typical I 2C Data Transfer Sequence6.3 Operation 6.3.1Write Cycle ExampleTable 6−1. I 2C Protocol Definitions Table 6−2. I 2C Address Byte Table6.3.2TAS3002 I2C Readback Example 6.3.3I2C Wait States6.4 SMBus Operation 6.4.1Block Write Protocol6.4.2Write Byte Protocol Table 6−3. I 2C Wait States6.4.3Wait States 6.4.4TAS3002 SMBus ReadbackPage 7.2 Power-Up/Power-DownReset 7.2.1Power-UpSequence7.2.2Reset 7 Microcontroller Operation7.2.3Reset Circuit Figure 7−1. TAS3002 Reset Circuit7.2.4Fast Load Mode TAS30027.3 Power-DownMode 7.2.5Codec Reset7.3.1Power-DownTiming Sequence Figure 7−2. Power-DownTiming Sequence7.4 Test Mode 7.5 Internal Interface7.6.2GPI Architecture Table 7−1. GPI Terminal ProgrammingFigure 7−3. Internal Interface Flow Chart Restore Volume and MCRStart Power Up Initialize Default EEPROM Slave Write GPI Power Down7.7 External EEPROM Memory Maps Table 7−2. 512-ByteEEPROM Memory Map 2.0 ChannelsADDRESS BYTE NUMBERFUNCTION TAS3002TAS3002 ADDRESS NUMBERFUNCTION CATEGORYTAS3002 ADDRESS NUMBERFUNCTION CATEGORY8.2 Recommended Operating Conditions 8 Electrical CharacteristicsStatic Digital Specifications Figure 8−1. ADC Digital Filter Characteristics 8.4 ADC Digital FilterFigure 8−4. ADC High-PassFilter Characteristics 8.5 Analog-to-DigitalConverter8.6 Input Multiplexer 8.7 DAC Interpolation Filter8.8 Digital-to-AnalogConverter 8.9 DAC Output Performance Data8.10 I2C Serial Port Timing Characteristics Figure 8−7. I 2C Bus Timing9 System Diagrams Figure 9−1. Stereo ApplicationTAS3002 ClockTAS3002 TAS3001Figure 9−2. TAS3002 Device, 2.1 Channels PLASTIC QUAD FLATPACK 10 Mechanical InformationPFB S-PQFP-G48 10−2