2 Audio Data Formats
2.1 Serial Interface Formats
The TAS3002 device works in master or slave mode.
In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external,
In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates. If the 512fS MCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate of 512fS must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied. In both cases, an LRCLK of 64SCLK must be supplied.
•MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.
•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I2S, right justified, and left justified. Table 2−1 indicates how the 13 options are selected using the I 2C bus and the main control register (MCR, I2C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS. Additionally, the
Table 2−1. Serial Interface Options
MODE | MCR BIT (6) | MCR BIT (5−4) | MCR BIT (1−0) | SERIAL INTERFACE | |
SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0 | |||||
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0 | 0 | 00 | 00 | ||
1 | 1 | 00 | 00 | ||
2 | 1 | 01 | 00 | ||
3 | 1 | 10 | 00 | ||
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| S | |
4 | 1 | 00 | 01 | ||
5 | 1 | 01 | 01 | ||
6 | 1 | 10 | 01 | ||
7 | 1 | 00 | 10 | ||
8 | 1 | 01 | 10 | ||
9 | 1 | 10 | 10 | ||
10 | 1 | 00 | 11 | ||
11 | 1 | 01 | 11 | ||
12 | 1 | 10 | 11 |
Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the different interface protocols.
2−1
