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Toshiba 3006GAL, 4006GAH, MK6006GAH 1. SCOPE, 2. GENERAL DESCRIPTION, Sales Number, Factory Number, MK3006GAL /MK4006GAH/MK6006GAH

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1. SCOPE

This document describes the specifications of the following model, MK3006GAL /MK4006GAH/MK6006GAH of 1.8- inch type Winchester disk drives.

.

Factory Number

Sales Number

HDD1442MK3006GAL

HDD1564MK4006GAH

HDD1544MK6006GAH

2. GENERAL DESCRIPTION

The MK3006GAL/MK4006GAH/MK6006GAH which is noted hereinafter as

“MK3006GAL/MK4006GAH/MK6006GAH” or as “ the drive ” comprises a series of intelligent disk drives .

The drive features an ATA-2 / 3 / 4 / 5 / 6 interface embedded controller that requires a simplified adapter board for interfacing to an AT or AT compatible bus. The drives employ Winchester technology and a closed loop servo control system which have made high recording density of 149.6 M bit/mm2(96.5G bit/in2)(MK3006GAL/MK6006GAH), 131.7 M bit/mm2(85.0G bit/in2)(MK4006GAH)and average access time of 15 msec with highest reliability of 300,000 hours for MTTF (Mean Time to Failure) possible.

The drive is distinctive for its small and light body.

The MK3006GAL/MK4006GAH/MK6006GAH consists of an HDA (Head Disk Assembly) and a printed circuit board. The HDA has a sealed module which contains a disk spindle assembly, a head actuator assembly and an air filtration system. This HDA adopts Winchester technology which enhances high reliability. The actuator is a rotary voice coil motor which enables high-speed access.

The disk is driven directly by a DC spindle motor. Air filtration is provided by a high performance air filtration system using both breather and circulation filters.

The drive provides a carriage lock mechanism which is activated automatically upon power down in order to prevent head/media from being damaged when it is not operating or under shipment.

The printed circuit board which is set externally to the HDA and equipped with all the electric circuitry necessary to operate the drive except the head drivers . The power supply and interface signal connectors are mounted on the board. Only the head control IC’s are located within the HDA. The circuitry perform the following functions:

Read/Write, Task File Control, Spindle Motor Control, Seek and Head Positioning Servo Control, Abnormal Condition Detection and Shock Sensor Control.

Toshiba Corporation Digital Media Network Company

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Contents

1.1.1.1.1.1.1.1 TOSHIBA Revision History 1.8 inch Hard Disk Drive MK6006GAH/4006GAH/3006GAL Product Specification Revision Date Initial issue ＳＡＦＥＴＹ IMPORTANT MESSAGES LIMITATION OF LIABILITY USAGE RESTRICTIONS SAFETY Page TABLE OF CONTENTS Page Page Table of Figures OWER URRENT RANSITION MK3006GAL D 1. SCOPE 2. GENERAL DESCRIPTION Page 3.KEY FEATURES 4. BASIC SPECIFICATION 5. PERFORMANCE 6. POWER REQUIREMENTS 6.1Supply Voltage 6.2 Power Consumption Figure 1 Power Current Transition 6.3 Energy Consumption Efficiency 7. MECHANICAL SPECIFICATIONS 7.1 Dimension and weight 7.2 Drive Orientation 7.3 Mounting Instructions 7.3.1 Installation Figure 2 MK3006GAL Dimensions Figure 3 MK6006GAH/MK4006GAH Dimensions 8. ENVIRONMENTAL LIMITS 8.1 Temperature and Humidity 8.1.1 Temperature 8.1.2 Humidity 8.2 Vibration Page 8.4 Altitude 8.5 Acoustics（Sound Power） 8.6 Safety Standards EMC Adaptability 8.7 Magnetic Fields 9. RELIABILITY 9.1 Error Rate 9.1.1 Non- Recoverable Error Rate 9.1.2 Seek Error Rate 9.2 Product Life 9.5 Load/Unload HOST INTERFACE 10.1 Cabling Interface Connector Cable length and capacitance DC input/output Characteristics 10.2.2.1 Input 10.2.2.2 Output 10.3 Interface connector 10.3.1 ATA interface connector 10.3.2 Pin Assignment 10.3.3 Signal Treatment 10.3.4 Series resistance 10.3.5 Signal Description I/O 10.4 Host Interface Timing 10.4.1 Program I/O Write Timing 10.4.2 Program I/O Read Timing 10.4.3 Multiword DMA Write Timing 10.4.4 Multiword DMA Read Timing 10.4.5 Ultra DMA Timing Sustained Ultra DMA data in burst Host pausing an Ultra DMA data in burst Device terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst Initiating an Ultra DMA data out burst Sustained Ultra DMA data out burst Device pausing an Ultra DMA data out burst Host terminating an Ultra DMA data out burst Device terminating an Ultra DMA data out burst Page 10.4.6 Reset Timing 10.5 Grounding 10.6 Address Decoding 10.7 Register Description 10.7.1 Data Register 10.7.1.1 Read/Write command 10.7.1.2 Read/Write Buffer command 10.7.1.3 Format command 10.7.2 Error Register 10.7.2.1 Operational Mode 10.7.2.2 Diagnostic Mode 10.7.3 Features Register (Write Precompensation Register) 10.7.3.1 Smart command 10.7.4 Sector Count Register 10.7.4.1 Disk Access command 10.7.4.2 Initialize Device Parameters command 10.7.5 Sector Number Register 10.7.6 Cylinder Low Registers 10.7.6.1 Disk Access command 10.7.6.2 SMART commands 10.7.7 Cylinder High Registers 10.7.8 Device/Head Register 10.7.9 Status Register 10.7.10 Command Register Command Code 10.7.11 Alternate Status Register 10.7.12 Device Control Register 10.7.13 Device Address register4 10.8 Command Descriptions 10.8.1 Nop (00h) 10.8.2 Recalibrate5 (1xh) 10.8.3 Flush Cache (E7h) 10.8.4 Flush Cache EXT (EAh) 10.8.5 Read Sector 10.8.6 Read Sector EXT 10.8.7 Write Sector 10.8.8 Write Sector EXT Page 10.8.9 Read Verify (40h) 10.8.10 Read Verify EXT 10.8.11 Write Verify6 (3Ch) 10.8.12 Format Track 10.8.13 Seek (7xh) 10.8.14 Toshiba Specific 10.8.15 Execute Diagnostics (90h) 10.8.16 Initialize Device Parameters (91h) 10.8.17 Download Microcode (92h) 10.8.18 Read Multiple 10.8.19 Read Multiple EXT (29h) 10.8.20 Write Multiple 10.8.21 Write Multiple EXT (39h) 10.8.22 Set Multiple Mode (C6h) 10.8.23 Read DMA 10.8.24 Read DMA EXT 10.8.25 Write DMA (CAh/CBh) 10.8.26 Write DMA EXT 10.8.27 Power Control (Exh) 10.8.27.1 Stand-byImmediate (E0/94) 10.8.27.2 Idle Immediate (E1/95) 10.8.27.3 Stand-by(E2/96) 10.8.27.4 Idle (E3/97) 10.8.27.5 Check Power Mode (E5/98) 10.8.27.6 Sleep (E6/99) 10.8.28 Read Buffer (E4h) 10.8.29 Write Buffer 10.8.30Identify Device (ECh) Page Page Page Page Page Page Page Page Page Page Page Page Page Page 10.8.31 SET MAX (F9h) Set Max Address 10.8.31.2 Set Max Set Password 10.8.31.3 Set Max Lock 10.8.31.4 Set Max Unlock 10.8.32 SET MAX ADDRESS EXT (37h) 10.8.33 Read Native Max Address (F8h) 10.8.34 Read Native Max Address EXT (27h) 10.8.35 Set Features (EFh) 10.8.36 SECURITY SET PASSWORD (F1h) 10.8.37 SECURITY UNLOCK (F2h) 10.8.38 SECURITY ERASE PREPARE (F3h) 10.8.39 SECURITY ERASE UNIT (F4h) 10.8.40 SECURITY FREEZE LOCK (F5h) 10.8.41 SECURITY DISABLE PASSWORD 10.8.42 SMART Function Set (B0h) SMART Read Attribute values Attribute Name Value Definition Self-testexecution status values Page SMART Read Attribute thresholds 10.8.42.3 SMART Enable Disable Attribute Autosave SMART Save Attribute Values SMART Execute Off-lineImmediate 10.8.42.5.2 Captive mode 10.8.42.5.3 SMART off-lineroutine 10.8.42.5.4 SMART Short self-testroutine 10.8.42.5.5 SMART Extended self-testroutine 10.8.42.5.6 SMART Selective self-testroutine Page SMART Read Log Sector 10.8.42.6.2 Summary error log sector SMART summary error log sector 10.8.42.6.2.1 Error log version 10.8.42.6.2.2 Error log data structure Error log data structure 10.8.42.6.2.3 Command data structure Command data structure 10.8.42.6.2.4 Error data structure Error data structure State field values 10.8.42.6.2.5 Device error count 10.8.42.6.2.6 Data structure checksum 10.8.42.6.3 Comprehensive error log Comprehensive error log 10.8.42.6.3.1 Error log version 10.8.42.6.3.4 Device error count 10.8.42.6.3.5 Data structure checksum 10.8.42.6.4 Self-testlog sector Self-testlog data structure 10.8.42.6.4.1 Self-testlog data structure revision number 10.8.42.6.4.2 Self-testlog descriptor entry Self-testlog descriptor entry 10.8.42.6.4.3 Self-testindex 10.8.42.6.4.4 Data structure checksum 10.8.42.6.5 Selective self-testlog Selective self-testlog Read/write 10.8.42.6.5.1 Data structure revision number 10.8.42.6.5.2 Test span definition 10.8.42.6.5.4 Current span under test 10.8.42.6.5.5 Feature flags Selective self-testfeature flags Bit 10.8.42.6.5.6 Selective self-testpending time 10.8.42.7 SMART Write Log Sector 10.8.42.8 SMART Enable Operations SMART Disable Operations SMART Return Status 10.8.42.11 SMART Enable/Disable Automatic Off-line 10.8.43 Read Log EXT (2Fh) 10.8.43.1 General Purpose Log Directory 10.8.43.2 Extended Comprehensive SMART Error log 10.8.43.2.2 Error log index 10.8.43.2.3 Extended Error log data structure Extended Error log data structure 10.8.43.2.3.1 Command data structure Command data structure 10.8.43.2.3.2 Error data structure Error data structure Byte Descriptions State field values State 10.8.43.2.4 Device error count 10.8.43.2.5 Data structure checksum 10.8.43.3 Extended Self-testlog sector 10.8.43.3.3 Extended Self-testlog descriptor entry Extended Self-testlog descriptor entry 10.8.43.3.4 Data structure checksum 10.8.44 Write Log EXT (3Fh) 10.8.45 Device Configuration (B1h) 10.8.45.1 Device Configuration Restore Device Configuration Identify 10.8.45.3.1.1 Word 0: Data structure revision 10.8.45.3.1.2 Word 1: Multiword DMA modes supported 10.8.45.3.1.3 Word 2: Ultra DMA modes supported 10.8.45.3.1.4 Words 3-6:Maximum LBA address 10.8.45.3.1.5 Word 7: Command/features set supported 10.8.45.3.1.6Words 8-254:Reserved 10.8.45.3.1.7Word 255: Integrity word Device Configuration Set 10.8.45.4.1 Error outputs Register 10.8.45.4.2 Description 10.8.45.4.2.1 Word 0: Data structure revision 10.8.45.4.2.2 Word 1: Multiword DMA modes supported 10.8.45.4.2.3 Word 2: Ultra DMA modes supported 10.8.45.4.2.4 Words 3-6:Maximum LBA address 10.8.45.4.2.5 Word 7: Command/features set supported 10.8.45.4.2.6Words 8-254:Reserved 10.8.45.4.2.7Word 255: Integrity word 10.9 Security Mode Feature Set 10.9.1 Security mode default setting 10.9.2 Initial setting of the user password 10.9.3 Security mode operation from power-on 10.9.4 Password lost 10.9.5 Command Table 10.10 Self-Monitoring,Analysis and Reporting Technology 10.10.1Attributes 10.10.2 Attributes values 10.10.3 SMART function default setting 10.11 Adaptive Power Mode Control 10.11.1 Performance Idle 10.11.2 Active Idle 10.11.3Low Power Idle 10.11.4Transition time 10.12 Reset 10.13 Drive0/Drive1 Configuration 10.14 Cache Memory 10.14.1 Cache Operations 10.14.2 Notes for write cache 10.15 Automatic Write Reallocation 11. Protocol 11.1 PIO data in commands 11.2 PIO data out commands 11.3 Non-datacommands 11.4 DMA data transfer commands 11.5 Ultra DMA Page Page 11.6 Other timings