R
Chapter 3: Quickstart Example Design
simulation/dsport
The dsport directory contains the data stream simulation scripts provided with the core.
Table 3-8: dsport Directory
Name | Description |
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<project_dir>/<component_name>/simulation/dsport
dsport_cfg.v[hd]
pci_exp_expect_tasks.v
pci_exp_1_lane_64b_dsport.v[hd] pci_exp_4_lane_64b_dsport.v[hd] pci_exp_usrapp_cfg.v[hd] pci_exp_usrapp_com.v pci_exp_usrapp_rx.v[hd] pci_exp_usrapp_tx.v[hd] xilinx_pci_exp_downstream_port.v[hd] xilinx_pci_exp_dsport.v[hd]
test_interface.vhd
Downstream port model files.
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simulation/functional
The functional directory contains functional simulation scripts provided with the core.
Table 3-9: Functional Directory
Name | Description | |
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<project_dir>/<component_name>/simulation/functional | ||
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board_rtl_x01_v4fx.f |
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board_rtl_x04_v4fx.f |
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board_rtl_x08_v4fx.f |
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board_rtl_x01_v4fx_ncv.f | List of files for RTL simulations. | |
board_rtl_x04_v4fx_ncv.f |
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board_rtl_x08_v4fx_ncv.f |
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board_rtl.f |
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simulate_mti.do | Simulation script for ModelSim. | |
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simulate_ncsim.sh | Simulation script for Cadence IUS. | |
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simulate_vcs.sh | Simulation script for VCS. | |
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xilinx_lib_vcs.f | Points to the required SmartModel. | |
xilinx_lib_vnc.f | ||
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24 | www.xilinx.com | Endpoint Block Plus v1.8 for PCI Express |
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| UG343 June 27, 2008 |
