Xilinx 1.8 simulation/dsport, simulation/functional

24 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express

UG343 June 27, 2008

Chapter 3: Quickstart Example Design

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simulation/dsport

The dsport directory contains the data stream simulation scripts provided with the core.

simulation/functional

The functional directory contains functional simulation scripts provided with the core.

Table 3-8: dsport Directory

Name Description

<project_dir>/<component_name>/simulation/dsport

dsport_cfg.v[hd]

pci_exp_expect_tasks.v

pci_exp_1_lane_64b_dsport.v[hd]

pci_exp_4_lane_64b_dsport.v[hd]

pci_exp_usrapp_cfg.v[hd]

pci_exp_usrapp_com.v

pci_exp_usrapp_rx.v[hd]

pci_exp_usrapp_tx.v[hd]

xilinx_pci_exp_downstream_port.v[hd]

xilinx_pci_exp_dsport.v[hd]

test_interface.vhd

Downstream port model files.

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Table 3-9: Functional Directory

Name Description

<project_dir>/<component_name>/simulation/functional

board_rtl_x01_v4fx.f

board_rtl_x04_v4fx.f

board_rtl_x08_v4fx.f

board_rtl_x01_v4fx_ncv.f

board_rtl_x04_v4fx_ncv.f

board_rtl_x08_v4fx_ncv.f

board_rtl.f

List of files for RTL simulations.

simulate_mti.do Simulation script for ModelSim.

simulate_ncsim.sh Simulation script for Cadence IUS.

simulate_vcs.sh Simulation script for VCS.

xilinx_lib_vcs.f

xilinx_lib_vnc.f Points to the required SmartModel.

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Contents

Main Revision History Table of Contents Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quickstart Example Design Appendix: Additional Design Considerations Preface About This Guide Contents Conventions Typographical Online Document Chapter 1 Introduction About the Core System Requirements Windows Linux Additional Core Resources Technical Support Feedback Core Document Page Chapter 2 Licensing the Core Before you Begin License Options Simulation Only Full Obtaining Your License Simulation Only Evaluation License Obtaining a Full License Installing Your License File Chapter 3 Quickstart Example Design Overview Simulation Design Overview Chapter 3: Quickstart Example Design Figure 3-1: Simulation Example Design Block Diagram Implementation Design Overview Example Design Elements Generating the Core Page Simulating the Example Design Setting up for Simulation Simulator Requirements Running the Simulation For Cadence IUS Implementing the Example Design Directory Structure and File Contents Example Design <project directory> <project directory>/<component name> <component name>/doc <component name>/example_design <component name>/implement implement/results <component name>/simulation simulation/dsport simulation/functional simulation/tests Dual Core Example Design Dual Core Directory Structure and File Contents <component name>/example_design example_design/dual_core <component name>/simulation simulation/functional <component name>/implement Appendix Additional Design Considerations Package Constraints User Constraints Files Wrapper File Usage