Xilinx 1.8 Generating the Core

16 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express

UG343 June 27, 2008

Chapter 3: Quickstart Example Design

Generating the Core

To generate a core using the default values in the CORE Generator Graphical User

Interface (GUI), do the following:

1. Start the CORE Generator.

For help starting and using the CORE Generator, see the Xilinx CORE Generator

Guide, available from the ISE documentation web page.

2. Choose File > New Project.

3. Enter a project name and location, then click OK. <project_dir> is used in this

example. The Project Options dialog box appears.

Figure 3-3: New Project Dialog Box

Figure 3-4: Project Options

Contents

Main Revision History Table of Contents Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quickstart Example Design Appendix: Additional Design Considerations Preface About This Guide Contents Conventions Typographical Online Document Chapter 1 Introduction About the Core System Requirements Windows Linux Additional Core Resources Technical Support Feedback Core Document Page Chapter 2 Licensing the Core Before you Begin License Options Simulation Only Full Obtaining Your License Simulation Only Evaluation License Obtaining a Full License Installing Your License File Chapter 3 Quickstart Example Design Overview Simulation Design Overview Chapter 3: Quickstart Example Design Figure 3-1: Simulation Example Design Block Diagram Implementation Design Overview Example Design Elements Generating the Core Page Simulating the Example Design Setting up for Simulation Simulator Requirements Running the Simulation For Cadence IUS Implementing the Example Design Directory Structure and File Contents Example Design <project directory> <project directory>/<component name> <component name>/doc <component name>/example_design <component name>/implement implement/results <component name>/simulation simulation/dsport simulation/functional simulation/tests Dual Core Example Design Dual Core Directory Structure and File Contents <component name>/example_design example_design/dual_core <component name>/simulation simulation/functional <component name>/implement Appendix Additional Design Considerations Package Constraints User Constraints Files Wrapper File Usage