Xilinx 1.8 <component name>/example_design, example_design/dual_core, <component name>/simulation

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 27
UG343 June 27, 2008
Dual Core Example Design
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<component name>/example_design
The example design directory includes the dual core example design ucf, which varies
based on the device selected.
example_design/dual_core
The dual core directory contains the top-level and wrapper files for the dual core example
design.
<component name>/simulation
The simulation directory includes the dual core example design simulation files.
Table 3-11: Example Design Directory
Name Description
xilinx_dual_*.ucf Dual core example design ucf. Varies by
lane-width, part, and package selected.
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Table 3-12: Dual Core Directory
Name Description
xilinx_dual_pci_exp_ep.v[hd] Verilog or VHDL top-level dual core PIO
example design file for 8-lane, 4-lane, and
1-lane dual cores.
xilinx_pci_exp_primary_ep.v[hd] Verilog or VHDL wrapper for the PIO
example design for 8-lane, 4-lane, and 1-
lane primary core.
xilinx_pci_exp_secondary_ep.v[hd] Verilog or VHDL wrapper for the PIO
example design for 8-lane, 4-lane, and 1-
lane secondary core.
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Table 3-13: Simulation Directory
Name Description
board_dual.v[hd] Top-level simulation module.
xilinx_dual_pci_exp_cor_ep.f List of files comprising the design being
tested.
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