Xilinx 1.8 Quickstart Example Design

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 13

UG343 June 27, 2008

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Chapter 3

Quickstart Example Design

This chapter provides an overview of the Endpoint Block Plus for PCI Express example

design (both single and dual core) and instructions for generating the core. It also includes

information about simulating and implementing the example design using the provided

demonstration test bench.

Overview

The example simulation design consists of two discrete parts:

•The Downstream Port Model, a test bench that generates, consumes, and checks PCI

Express bus traffic.

•The Programmed Input Output (PIO) example design, a completer application for PCI

Express. The PIO example design responds to Read and Write requests to its memory

space and can be synthesized for testing in hardware.

Simulation Design Overview

For the simulation design, transactions are sent from the Downstream Port Model to the

Block Plus core and processed by the PIO example design. Figure3-1 illustrates the

simulation design provided with the Block Plus core. For more information about the

Downstream Port Model, see Appendix B, “Downstream Port Model Test Bench,” in the

LogiCORE IP Endpoint Block Plus for PCI Express User Guide.

Contents

Main Revision History Table of Contents Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quickstart Example Design Appendix: Additional Design Considerations Preface About This Guide Contents Conventions Typographical Online Document Chapter 1 Introduction About the Core System Requirements Windows Linux Additional Core Resources Technical Support Feedback Core Document Page Chapter 2 Licensing the Core Before you Begin License Options Simulation Only Full Obtaining Your License Simulation Only Evaluation License Obtaining a Full License Installing Your License File Chapter 3 Quickstart Example Design Overview Simulation Design Overview Chapter 3: Quickstart Example Design Figure 3-1: Simulation Example Design Block Diagram Implementation Design Overview Example Design Elements Generating the Core Page Simulating the Example Design Setting up for Simulation Simulator Requirements Running the Simulation For Cadence IUS Implementing the Example Design Directory Structure and File Contents Example Design <project directory> <project directory>/<component name> <component name>/doc <component name>/example_design <component name>/implement implement/results <component name>/simulation simulation/dsport simulation/functional simulation/tests Dual Core Example Design Dual Core Directory Structure and File Contents <component name>/example_design example_design/dual_core <component name>/simulation simulation/functional <component name>/implement Appendix Additional Design Considerations Package Constraints User Constraints Files Wrapper File Usage