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Xilinx 1.8 Dual Core Directory Structure and File Contents

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UG343 June 27, 2008

Chapter 3: Quickstart Example Design

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Dual Core Directory Structure and File Contents

When g ene rat ing t he B loc k Pl us co re w ith the Virtex-5 FX70T-FF1136 (XC5VFX70T-FF1136)

FPGA, the PIO example design source files and scripts are generated using the directory

structure specified in the “Directory Structure and File Contents” section.

For the dual core example design, in addition to the source files, simulation scripts, and

implementation files generated in the <project name>/<component name> directory

specified by the user, the following directories and associated files are used:

<component name>/example_design

Dual core Verilog or VHDL design files

example_design/dual_core

Implementation script files

<component name>/simulation

Simulation Verilog or VHDL source files

simulation/functional

Simulation scripts

<component name>/implement

Implementation scripts

Figure 3-6: Dual Core Design Block Diagram

xilinx_dual_pci_exp_ep

pci_exp_64b_app

Endpoint

Core

xilinx_pci_exp_primary_ep

PIO

pci_exp_64b_app

Endpoint

Core

xilinx_pci_exp_secondary_ep

PIO

Contents

Main Revision History Table of Contents Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quickstart Example Design Appendix: Additional Design Considerations Preface About This Guide Contents Conventions Typographical Online Document Chapter 1 Introduction About the Core System Requirements Windows Linux Additional Core Resources Technical Support Feedback Core Document Page Chapter 2 Licensing the Core Before you Begin License Options Simulation Only Full Obtaining Your License Simulation Only Evaluation License Obtaining a Full License Installing Your License File Chapter 3 Quickstart Example Design Overview Simulation Design Overview Chapter 3: Quickstart Example Design Figure 3-1: Simulation Example Design Block Diagram Implementation Design Overview Example Design Elements Generating the Core Page Simulating the Example Design Setting up for Simulation Simulator Requirements Running the Simulation For Cadence IUS Implementing the Example Design Directory Structure and File Contents Example Design <project directory> <project directory>/<component name> <component name>/doc <component name>/example_design <component name>/implement implement/results <component name>/simulation simulation/dsport simulation/functional simulation/tests Dual Core Example Design Dual Core Directory Structure and File Contents <component name>/example_design example_design/dual_core <component name>/simulation simulation/functional <component name>/implement Appendix Additional Design Considerations Package Constraints User Constraints Files Wrapper File Usage