Directory Structure and File Contents | Xilinx 1.8 manual

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Chapter 3: Quickstart Example Design

•routed.sdf

Timing model Standard Delay File.

•mapped.mrp

Xilinx map report.

•routed.par

Xilinx place and route report.

•routed.twr

Xilinx timing analysis report.

The script file starts from an EDIF/NGC file and results in a bitstream file. It is possible to use the Xilinx ISE GUI to implement the example design. However, the GUI flow is not presented in this document.

Directory Structure and File Contents

The Endpoint Block Plus for PCIe example design directories and their associated files are defined in the sections that follow. Click a directory name to go to the desired directory and its associated files.

Example Design

<project directory>

Top-level project directory; name is user-defined

<project directory>/<component name>

Core release notes readme file

<component name>/doc

Product documentation

<component name>/example_design

Verilog or VHDL design files

<component name>/implement

Implementation script files

implement/results

Results directory, created after implementation scripts are run, and contains implement script results

<component name>/simulation

Simulation scripts

simulation/dsport

Simulation files

simulation/functional

Functional simulation files

simulation/tests

Test command files

Note: For the dual core example design directory structure and file contents, see “Dual Core Directory Structure and File Contents,” page 26.

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Xilinx 1.8 manual Directory Structure and File Contents

Contents

LogiCORE IP Endpoint Block Plus v1.8 for PCI Express UG343 June 27 Revision History Date Version Revision Table of Contents Appendix Additional Design Considerations Conventions ContentsAbout This Guide Online Document Preface About This Guide Introduction About the CoreSystem Requirements Recommended Design Experience Additional Core Resources Technical SupportFeedback Core Document Feedback Introduction Licensing the Core Before you BeginLicense Options Simulation Only Licensing the Core Installing Your License FileObtaining Your License Simulation Design Overview Quickstart Example DesignOverview 1Simulation Example Design Block Diagram Quickstart Example Design Overview Implementation Design OverviewExample Design Elements Generating the Core 3New Project Dialog Box Generating the Core 5Endpoint Block Plus Main Screen Running the Simulation Setting up for SimulationSimulating the Example Design Implementing the Example Design Implementing the Example DesignWindows Linux Directory Structure and File Contents Component name/doc Project directoryProject directory/component name Component name/exampledesign Component name/implement4Example Design Directory Name Description 5Implement Directory Name Description Implement/results Component name/simulation6Results Directory Name Description 7Simulation Directory Name Description Simulation/dsport Simulation/functional8dsport Directory Name Description 9Functional Directory Name Description Dual Core Example Design Simulation/testsDual Core Example Design 10Tests Directory Name Description Dual Core Directory Structure and File Contents Exampledesign/dualcore 11Example Design Directory Name Description12Dual Core Directory Name Description 13Simulation Directory Name Description 14Functional Directory Name Description 15Implement Directory Name Description Package Constraints User Constraints FilesWrapper File Usage Device/Part Number Appendix Appendix Additional Design Considerations