Intel IQ80321 manual Exceptions/Trapping

Page 103

Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started and Debugger

B.9.3 Exceptions/Trapping

A debug exception causes the processor to re-direct execution to a debug event handling routine.

The Intel® 80200 processor debug architecture defines the following debug exceptions:

•instruction breakpoint

•data breakpoint

•software breakpoint

•external debug break

•exception vector trap

•trace-buffer full break

When a debug exception occurs, the processor actions depend on whether the debug unit is configured for Halt mode or Monitor mode.

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Contents Board Manual Intel IQ80321 I/O Processor Evaluation PlatformBoard Manual Intel IQ80321 I/O Processor Evaluation PlatformContents Debug Interface Dram 100 119 Figures Tables 105 Description Revision HistoryThis page intentionally left blank Related Documents Document Purpose and ScopeComponent Reference Electronic InformationComponent References Electronic InformationTerms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Intel 80321 I/O Processor Block DiagramIntel IQ80321 I/O Processor Evaluation Platform Summary of Features Intel IQ80321 Evaluation Platform Board FeaturesFeature Definition Power and Backplane Requirements Kit ContentHardware Installation First-Time Installation and TestSupported Tool Buckets Factory SettingsContents of the Flash Development StrategyTarget Monitors Redhat RedbootARM Firmware Suite Semihosting File I/O ARM AngelSerial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationGNUPro GDB/Insight Communicating with RedbootIntel IQ80321 I/O Processor Evaluation Platform GDB set remotebaud Connecting with GDBARM Extended Debugger This page intentionally left blank Intel Functional DiagramBoard Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerSupported Dimm Types Battery BackupDDR Memory Features Memory SubsystemFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode 80321 I/O Processor Interrupt RoutingIntel IQ80321 Evaluation Platform Board Peripheral Bus Peripheral Bus FeaturesFlash ROM Flash ROM FeaturesUart Uart FeaturesHEX Display on the Peripheral Bus HEX DisplayRotary Switch Requirements Rotary SwitchBattery Status Buffer Requirements Battery StatusIntel 82544EI Gigabit Ethernet Controller Debug InterfaceConsole Serial Port Ethernet PortJtag Port Pin-out Logic-Analyzer ConnectorsJtag Debug 3.1 Jtag PortMictor J3F2 Micor J3F2 Signal/PinsSchematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Mictor J1C1 Micor J1C1 Signal/PinsMictor J3C1 Micor J3C1 Signal/PinsMictor J2C1 Micor J2C1 Signal/PinsReset Requirements/Schemes Board Reset SchemeReset Sources Switch Summary Switches and JumpersPCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsSwitch S7E1- 2/3 Detail Descriptions of Switches/JumpersSwitch S7E1- 6/7 Switch S7E1- 4/5S7E1-8 Switch S7E1Switch S7E1 8 Descriptions Switch S7E1 8 Settings and Operation ModeSwitch S8E1 Switch S8E1 6 Descriptions Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 5 Driver Mode Output ImpedancesSwitch S8E1 8 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 DescriptionsSwitch S8E2 Switch S8E2 1/2Switch S9E1 4 Descriptions Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 13 Settings and Operation ModeSwitch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9F1 Jumper J9E1This page intentionally left blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device ConfigurationParameter Voltages DramComponents on the Peripheral Bus DDR Memory Bias Voltage Minimum/Maximum ValuesSoftware Reference Address Read Register Write Register Uart Register SettingsHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Physical Address Range Description Redboot* Intel IQ80321 Memory MapRedboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Physical Memory Map VisualRedboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Virtual Memory Map VisualRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Purpose IntroductionNecessary Hardware and Software Related Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashRunning the CodeLab Debugger Launching and Configuring DebuggerDisplaying Source Code Manually Loading and Executing an Application ProgramUsing Breakpoints Stepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Hardware Breakpoints Debugging BasicsHardware and Software Breakpoints Software BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping