Intel IQ80321 manual Board Form-Factor/Connectivity, Form-Factor/Connectivity Features

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Intel® IQ80321 I/O Processor Evaluation Platform

Hardware Reference Section

3.2Board Form-Factor/Connectivity

Table 6 summarizes the form-factor and connectivity features for the IQ80321.

Table 6. Form-Factor/Connectivity Features

Description

The Intel® IQ80321 Evaluation Platform Board is a full-size PCI card with form factor depicted by Figure 6.

The IQ80321s connects to the Primary PCI-X (PPCI-X) bus a PCI-X.

The IQ80321 has one PCI-X expansion slot.

The IQ80321 uses the Intel® 82544 Gigabit Ethernet Controller for network connectivity.

The IQ80321 can electrically isolate the Intel® 82544 Gigabit Ethernet Controller on the SPCI-X bus using user switches.

The IQ80321 has one serial port/UART (compatible with 16C550).

The IQ80321 has one JTAG port compliant with ARM Multi-ICE 20-pin connector standard. The JTAG is targeted for the Intel® XScale™ core and is used for software debug purposes.

Figure 6. Board Form Factor

	Secondary PCI-X Connector
			HEX Display		JTAG
					JTAG
	Logic Analyzer Connectors
	Intel®	Intel®	80321	Connector
	82544	Intel®	80321
		I/O Processor			User Switches
	Network	I/O Processor		DIMM
	Network
	Connector
	Logic Analyzer Connectors
	Logic Analyzer Connectors			DDR
				DDR	Battery
	Serial Connector
	FLASH	PCI-X
	FLASH	Bridge
	Rotary
					A9449-02

32	Board Manual

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Contents Intel IQ80321 I/O Processor Evaluation Platform Board ManualIntel IQ80321 I/O Processor Evaluation Platform Board ManualContents Debug Interface Dram 100 119 Figures Tables 105 Revision History DescriptionThis page intentionally left blank Document Purpose and Scope Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceDefinition Terms and DefinitionsTerms and Definitions Intel 80321 I/O Processor Block Diagram Intel 80321 I/O ProcessorIntel IQ80321 I/O Processor Evaluation Platform Feature Definition Intel IQ80321 Evaluation Platform Board FeaturesSummary of Features Kit Content Hardware InstallationFirst-Time Installation and Test Power and Backplane RequirementsFactory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OEthernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightIntel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaudARM Extended Debugger This page intentionally left blank Functional Diagram IntelForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup DDR Memory FeaturesMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O ProcessorPeripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsDebug Interface Console Serial PortEthernet Port Intel 82544EI Gigabit Ethernet ControllerLogic-Analyzer Connectors Jtag Debug3.1 Jtag Port Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Mictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Reset Sources Board Reset SchemeReset Requirements/Schemes Switches and Jumpers Switch SummaryPcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary Secondary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 Switch S7E1 8 DescriptionsSwitch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Descriptions Switch S8E1 5 Settings and Operation ModeSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Descriptions Switch S8E1 7 Settings and Operation ModeSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 Switch S9E1 13 DescriptionsSwitch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9E1 Jumper J9F1This page intentionally left blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceDram Components on the Peripheral BusDDR Memory Bias Voltage Minimum/Maximum Values Parameter VoltagesSoftware Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range DescriptionRedboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Necessary Hardware and Software IntroductionPurpose Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping